21 lines
352 B
Coq
21 lines
352 B
Coq
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// SystemVerilog allows parameters without default values in the parameter port
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// list. Check that this is supported. The test should fail in Verilog mode.
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module a #(
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parameter A
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);
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initial begin
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if (A == 1) begin
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$display("PASSED");
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end else begin
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$display("FAILED");
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end
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end
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endmodule
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module test;
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a #(.A(1)) i_a();
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endmodule
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