52 lines
1.2 KiB
VHDL
52 lines
1.2 KiB
VHDL
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library ieee;
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use ieee.std_logic_1164.all;
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-- This is a simple test of the initialization assignment for
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-- signals. We also let a generic into the test.
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entity test is
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generic (width : integer := 4);
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port (clk : in std_logic;
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src0, src1 : in std_logic_vector (width-1 downto 0);
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dst : out std_logic_vector (width-1 downto 0));
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end test;
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library ieee;
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use ieee.std_logic_1164.all;
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entity reg_xor is
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port (clk : in std_logic;
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src0, src1 : in std_logic;
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dst : out std_logic);
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end reg_xor;
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architecture operation of test is
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component reg_xor
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port (clk : in std_logic;
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src0, src1 : in std_logic;
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dst : out std_logic);
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end component;
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begin
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vec: for idx in width-1 downto 0 generate
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slice: reg_xor port map (clk => clk,
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src0 => src0(idx),
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src1 => src1(idx),
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dst => dst(idx));
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end generate vec;
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end operation;
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architecture operation of reg_xor is
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signal tmp : std_logic;
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begin
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tmp <= src0 xor src1;
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step: process (clk)
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begin -- process step
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if clk'event and clk = '1' then -- rising clock edge
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dst <= tmp;
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end if;
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end process step;
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end operation;
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