14 lines
322 B
Coq
14 lines
322 B
Coq
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module top;
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reg [4:0]cntr;
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wire done;
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wire allone;
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// A delayed comparison is only 1 bit wide. If this does not crash
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// the run time then the compiler is producing correct code.
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assign #1 done = cntr == 'd7;
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// The same for a reduction.
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assign #1 allone = &cntr;
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initial $display("PASSED");
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endmodule
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