iverilog/ivtest/ivltests/cond_wide.v

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/*
* Copyright (c) 2001 Stephen Williams (steve@icarus.com)
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
/*
* This progam catches the case where the truth value is really the
* reduction-OR of the condition expression, and not just the low bit.
*/
module test;
reg [1:0] foo = 2'b10;
initial #1 begin
while (foo) begin
$display("PASSED");
$finish;
end
$display("FAILED -- foo = %b", foo);
end
endmodule // test