17 lines
236 B
Coq
17 lines
236 B
Coq
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`timescale 1ns/1ns
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module top;
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real rtrig = 0.0;
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wire real rtm;
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assign rtm = rtrig * $realtime;
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initial begin
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$monitor(rtm);
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#1 rtrig = 1.0;
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#1 rtrig = 0.0;
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#1 rtrig = 1.0;
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#1 rtrig = 0.0;
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end
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endmodule
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