60 lines
1.1 KiB
Coq
60 lines
1.1 KiB
Coq
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module testr(input clk, output real out, input wire real in);
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always @(posedge clk)
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out <= in + 1.0;
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endmodule // testr
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module testi(input clk, output int out, input wire int in);
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always @(posedge clk)
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out <= in + 1;
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endmodule // testi
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module main;
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reg clk;
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always begin
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#10 clk = 0;
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#10 clk = 1;
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end
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real srcr;
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int srci;
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wire real valr;
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wire int vali;
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testr r0 (.clk(clk), .out(valr), .in(srcr));
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testi i0 (.clk(clk), .out(vali), .in(srci));
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real refr;
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int refi;
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always @(posedge clk) begin
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refr <= srcr + 1.0;
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refi <= srci + 1;
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end
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initial begin
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@(negedge clk) ;
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srcr = 2.0;
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srci = 2;
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@(negedge clk) ;
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@(negedge clk) ;
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$display("srcr=%f, valr=%f, refr=%f", srcr, valr, refr);
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if (valr != refr && valr != 3.0) begin
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$display("FAILED");
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$finish;
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end
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$display("srci=%0d, vali=%0d, refi=%0d", srci, vali, refi);
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if (vali != refi && vali != 3) begin
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$display("FAILED");
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$finish;
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end
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$display("PASSED");
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$finish;
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end
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endmodule // main
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