15 lines
249 B
Coq
15 lines
249 B
Coq
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module top;
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initial begin
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// In SystemVerilog a function is not required to return a value or
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// to take an argument.
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test_fcn();
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$display("PASSED");
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end
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function bit test_fcn();
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test_fcn = 1'b1;
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endfunction
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endmodule
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