102 lines
2.9 KiB
ReStructuredText
102 lines
2.9 KiB
ReStructuredText
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Using The Verilog '95 Code Generator
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====================================
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Icarus Verilog contains a code generator to emit 1995 compliant Verilog from
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the input Verilog netlist. This allows Icarus Verilog to function as a Verilog
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> 1995 to Verilog 1995 translator. The main goal of the project was to convert
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@*, ANSI style arguments and other constructs to something allowed in 1995
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Verilog.
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Invocation
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----------
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To translate a Verilog program to 1995 compliant Verilog, invoke "iverilog"
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with the -tvlog95 flag::
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% iverilog -tvlog95 -o my_design_95.v my_design.v
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The generated Verilog will be placed in a single file (a.out by default), even
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if the input Verilog is spread over multiple files.
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Generator Flags
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---------------
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* -pspacing=N
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Set the indent spacing (the default is 2).
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* -pallowsigned=1
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Allow emitting the various signed constructs as an extension to 1995 Verilog
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(off by default).
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* -pfileline=1
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Emit the original file and line information as a comment for each generated
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line (off by default).
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Structures that cannot be converted to 1995 compatible Verilog
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--------------------------------------------------------------
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The following Verilog constructs are not translatable to 1995 compatible Verilog:
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* Automatic tasks or functions.
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* The power operator (**). Expressions of the form (2**N)**<variable> (where N
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is a constant) can be converter to a shift.
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* Some System Verilog constructs (e.g. final blocks, ++/-- operators,
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etc.). 2-state variables are converted to 4-state variables.
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Icarus extensions that cannot be translated:
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* Integer constants greater than 32 bits.
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* Real valued nets.
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* Real modulus.
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* Most Verilog-A constructs.
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Known Issues and Limitations
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----------------------------
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Some things are just not finished and should generate an appropriate
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warning. Here is a list of the major things that still need to be looked at.
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* There are still a few module instantiation port issues (pr1723367 and
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partselsynth).
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* inout ports are not converted (tran-VP).
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* Variable selects of a non-zero based vector in a continuous assignment are
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not converted.
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* There is no support for translating a zero repeat in a continuous
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assignment. It is currently just dropped.
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* A pull device connected to a signal select is not translated correctly (this
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may be fixed).
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* L-value indexed part selects with a constant undefined base in a continuous
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assignment are not translated.
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* Logic gates are not arrayed exactly the same as the input and the instance
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name is not always the same.
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* The signed support does not generate $signed() or $unsigned() function calls
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in a continuous assignment expression.
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* The special power operator cases are not converted in a continuous
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assignment.
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* Currently a signed constant that sets the MSB in an unsigned context will be
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displayed as a negative value (e.g. bit = 1 translates to bit = -1).
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* Can net arrays, etc. be unrolled?
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* Can generate blocks be converted?
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