iverilog/Documentation/targets/index.rst


The Icarus Verilog Targets
==========================

Icarus Verilog elaborates the design, then sends to the design to code
generates (targets) for processing. new code generators can be added by
external packages, but these are the code generators that are bundled with
Icarus Verilog. The code generator is selected by the "-t" command line flag.

.. toctree::
   :maxdepth: 1

   vvp
   stub
   null
   vhdl
   verilog95
   pcb
Start Icarus Verilog Documentation using Sphinx Embed the Icarus Verilog documentation, and format it so that the Sphinx tools can process it into html or other formats. This will make the documentation easier to keep up to date with the actual software. 2022-04-11 03:19:30 +02:00
			`The Icarus Verilog Targets`
			`==========================`

			`Icarus Verilog elaborates the design, then sends to the design to code`
			`generates (targets) for processing. new code generators can be added by`
			`external packages, but these are the code generators that are bundled with`
			`Icarus Verilog. The code generator is selected by the "-t" command line flag.`

			`.. toctree::`
			`:maxdepth: 1`

			`vvp`
			`stub`
			`null`
Documentation: Transferring more content from the wiki This finishes up most of the User Guide from the Wiki. Some bits from the wiki are just too aweful, or obsolete, so are left out. 2022-04-12 05:46:06 +02:00			`vhdl`
			`verilog95`
			`pcb`