iverilog/netvector.h

109 lines
3.6 KiB
C
Raw Normal View History

#ifndef IVL_netvector_H
#define IVL_netvector_H
/*
2025-10-21 07:45:05 +02:00
* Copyright (c) 2012-2025 Stephen Williams (steve@icarus.com)
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
*/
# include "nettypes.h"
# include "ivl_target.h"
# include <vector>
2012-09-23 18:28:49 +02:00
class netvector_t : public ivl_type_s {
public:
explicit netvector_t(const netranges_t&packed, ivl_variable_type_t type);
// special case: there is a single packed dimension and we
// know it in the form [<msb>:<lsb>]. This step saves me
// creating a netrange_t for this single item.
explicit netvector_t(ivl_variable_type_t type, long msb, long lsb,
bool signed_flag =false);
// Special case: scalar object--no packed dimensions at all.
explicit netvector_t(ivl_variable_type_t type);
2025-10-21 07:45:05 +02:00
~netvector_t() override;
// Vectors can be interpreted as signed or unsigned when
// handled as vectors.
inline void set_signed(bool flag) { signed_ = flag; }
2025-10-21 07:45:05 +02:00
inline bool get_signed(void) const override { return signed_; }
inline void set_isint(bool flag) { isint_ = flag; }
inline bool get_isint(void) const { return isint_; }
2025-10-21 07:45:05 +02:00
inline bool get_scalar(void) const override { return packed_dims_.empty(); }
void set_implicit(bool implicit) { implicit_ = implicit; }
bool get_implicit() const { return implicit_; }
2025-10-21 07:45:05 +02:00
ivl_variable_type_t base_type() const override;
const netranges_t&packed_dims() const;
2025-10-21 07:45:05 +02:00
bool packed(void) const override;
long packed_width() const override;
netranges_t slice_dimensions() const override;
2025-10-21 07:45:05 +02:00
std::ostream& debug_dump(std::ostream&) const override;
public:
// Some commonly used predefined types
static netvector_t atom2s64;
static netvector_t atom2u64;
static netvector_t atom2s32;
static netvector_t atom2u32;
static netvector_t atom2s16;
static netvector_t atom2u16;
static netvector_t atom2s8;
static netvector_t atom2u8;
Correctly handle separate port type declaration for `integer` and `time` When using non-ANSI style port declarations it is possible to declare the port direction and the data type for the port in separate statements. E.g. ``` input x; reg x; ``` When using packed array dimensions they must match for both declarations. E.g. ``` input [3:0] x; reg [3:0] x; ``` But this only applies for vector types, i.e. the packed dimension is explicitly declared. It does not apply to the `integer` and `time` types, which have an implicit packed dimension. The current implementation requires that even for `integer` and `time` types the implicit dimension needs to be explicitly declared in the port direction. E.g. the following will result in a elaboration error complaining about a packed dimension mismatch. ``` module test; output x; integer x; endmodule ``` Currently the parser creates a vector_type_t for `time` and `integer`. This means that e.g. `time` and `reg [63:0]` are indistinguishable during elaboration, even though they require different behavior. To fix let the atom2_type_t handle `integer` and `time`. Since it no longer exclusively handles 2-state types, rename it to atom_type_t. This also fixes a problem with the vlog95 target unit tests. The vlog95 target translates ``` module test(output integer x); endmodule ``` to ``` module test(x); output x; integer x; endmodule ``` which then fails when being elaborated again. There were some regression tests that were failing because of this that will now pass. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2022-03-12 21:10:19 +01:00
static netvector_t time_signed;
static netvector_t time_unsigned;
static netvector_t scalar_bool;
static netvector_t scalar_logic;
Correctly handle separate port type declaration for `integer` and `time` When using non-ANSI style port declarations it is possible to declare the port direction and the data type for the port in separate statements. E.g. ``` input x; reg x; ``` When using packed array dimensions they must match for both declarations. E.g. ``` input [3:0] x; reg [3:0] x; ``` But this only applies for vector types, i.e. the packed dimension is explicitly declared. It does not apply to the `integer` and `time` types, which have an implicit packed dimension. The current implementation requires that even for `integer` and `time` types the implicit dimension needs to be explicitly declared in the port direction. E.g. the following will result in a elaboration error complaining about a packed dimension mismatch. ``` module test; output x; integer x; endmodule ``` Currently the parser creates a vector_type_t for `time` and `integer`. This means that e.g. `time` and `reg [63:0]` are indistinguishable during elaboration, even though they require different behavior. To fix let the atom2_type_t handle `integer` and `time`. Since it no longer exclusively handles 2-state types, rename it to atom_type_t. This also fixes a problem with the vlog95 target unit tests. The vlog95 target translates ``` module test(output integer x); endmodule ``` to ``` module test(x); output x; integer x; endmodule ``` which then fails when being elaborated again. There were some regression tests that were failing because of this that will now pass. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2022-03-12 21:10:19 +01:00
static const netvector_t*integer_type(bool is_signed = true);
private:
2025-10-21 07:45:05 +02:00
bool test_compatibility(ivl_type_t that) const override;
bool test_equivalence(ivl_type_t that) const override;
private:
netranges_t packed_dims_;
ivl_variable_type_t type_;
bool signed_ : 1;
bool isint_ : 1; // original type of integer
bool implicit_ : 1;
};
inline netvector_t::netvector_t(const netranges_t &pd,
ivl_variable_type_t type)
2022-12-28 08:59:39 +01:00
: packed_dims_(pd), type_(type), signed_(false), isint_(false), implicit_(false)
{
}
inline const netranges_t& netvector_t::packed_dims() const
{
return packed_dims_;
}
inline static std::ostream& operator << (std::ostream&out, const netvector_t&obj)
{
return obj.debug_dump(out);
}
#endif /* IVL_netvector_H */