94 lines
3.0 KiB
Coq
94 lines
3.0 KiB
Coq
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/*
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* Copyright (c) 2000 Stephen Williams (steve@icarus.com)
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*
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* This source code is free software; you can redistribute it
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* and/or modify it in source code form under the terms of the GNU
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* General Public License as published by the Free Software
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* Foundation; either version 2 of the License, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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/*
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* This example shows how to use Icarus Verilog to generate PLD output.
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* The design is intended to fit into a 22v10 in a PLCC package, with
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* pin assignments locked down by design.
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*/
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/*
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* The register module is an 8 bit register that copies the input to
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* the output registers on the rising edge of the clk input. The output
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* drivers are controled by a single active low output enable.
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*
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* This module contains all the logic of the device, but includes nothing
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* that has anything to do with the real hardware.
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*/
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module register (out, val, clk, oe);
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output [7:0] out;
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input [7:0] val;
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input clk, oe;
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reg [7:0] Q;
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wire [7:0] out;
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bufif0 drv[7:0](out, Q, oe);
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always @(posedge clk) Q = val;
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endmodule
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/*
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* The module pal is used to attach pin information to all the pins of
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* the device. We use this to lock down the pin assignments of the
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* synthesized result. The pin number assignments are for a 22v10 in
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* a PLCC package.
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*/
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module pal;
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wire out7, out6, out5, out4, out3, out2, out1, out0;
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wire inp7, inp6, inp5, inp4, inp3, inp2, inp1, inp0;
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wire clk, oe;
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// The PAD attributes attach the wires to pins of the
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// device. Output pins are prefixed by a 'o', and input pins by an
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// 'i'. If not all the available output pins are used, then the
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// remaining are available for the synthesizer to drop internal
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// registers or extra logic layers.
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$attribute(out7, "PAD", "o27");
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$attribute(out6, "PAD", "o26");
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$attribute(out5, "PAD", "o25");
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$attribute(out4, "PAD", "o24");
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$attribute(out3, "PAD", "o23");
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$attribute(out2, "PAD", "o21");
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$attribute(out1, "PAD", "o20");
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$attribute(out0, "PAD", "o19");
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$attribute(inp7, "PAD", "i10");
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$attribute(inp6, "PAD", "i9");
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$attribute(inp5, "PAD", "i7");
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$attribute(inp4, "PAD", "i6");
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$attribute(inp3, "PAD", "i5");
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$attribute(inp2, "PAD", "i4");
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$attribute(inp1, "PAD", "i3");
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$attribute(inp0, "PAD", "i2");
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//$attribute(clk, "PAD", "CLK");
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$attribute(oe, "PAD", "i13");
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register dev({out7, out6, out5, out4, out3, out2, out1, out0},
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{inp7, inp6, inp5, inp4, inp3, inp2, inp1, inp0},
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clk, oe);
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endmodule // pal
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