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27 lines
342 B
Verilog
27 lines
342 B
Verilog
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module test;
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function f_0;
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input i;
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begin
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f_0 = f_1(i);
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end
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endfunction
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function f_1;
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input i;
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begin
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f_1 = !i;
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end
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endfunction
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wire w = f_0(1'b0);
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initial begin
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#1;
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if ( w !== 1'b1)
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$display ("FAILED w (%b) !== 1'b1", w);
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else
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$display ("PASSED");
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end
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endmodule
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