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<!DOCTYPE html>
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<html lang="en" data-content_root="../">
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<title>Icarus Verilog Extensions — Icarus Verilog documentation</title>
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<link rel="next" title="Icarus Verilog Quirks" href="icarus_verilog_quirks.html" />
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<meta name="viewport" content="width=device-width, initial-scale=0.9, maximum-scale=0.9" />
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</head><body>
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<div class="document">
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<div class="documentwrapper">
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<div class="body" role="main">
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<section id="icarus-verilog-extensions">
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<h1>Icarus Verilog Extensions<a class="headerlink" href="#icarus-verilog-extensions" title="Link to this heading">¶</a></h1>
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<p>Icarus Verilog supports certain extensions to the baseline IEEE 1364
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standard. Some of these are picked from extended variants of the
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language, such as SystemVerilog, and some are expressions of internal
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behavior of Icarus Verilog, made available as a tool debugging aid.</p>
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<p>Don’t use any of these extensions if you want to keep your code portable
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across other Verilog compilers.</p>
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<section id="system-functions">
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<h2>System Functions<a class="headerlink" href="#system-functions" title="Link to this heading">¶</a></h2>
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<section id="is-signed-expr">
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<h3><code class="docutils literal notranslate"><span class="pre">$is_signed(<expr>)</span></code><a class="headerlink" href="#is-signed-expr" title="Link to this heading">¶</a></h3>
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<p>This function returns 1 if the expression contained is signed, or 0 otherwise.
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This is mostly of use for compiler regression tests.</p>
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</section>
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<section id="bits-expr-sizeof-expr">
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<h3><code class="docutils literal notranslate"><span class="pre">$bits(<expr>)</span></code>, <code class="docutils literal notranslate"><span class="pre">$sizeof(<expr>)</span></code><a class="headerlink" href="#bits-expr-sizeof-expr" title="Link to this heading">¶</a></h3>
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<p>The <code class="docutils literal notranslate"><span class="pre">$bits</span></code> system function returns the size in bits of the expression that
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is its argument. The result of this function is undefined if the argument
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doesn’t have a self-determined size.</p>
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<p>The <code class="docutils literal notranslate"><span class="pre">$sizeof</span></code> system function is deprecated in favour of <code class="docutils literal notranslate"><span class="pre">$bits</span></code>, which is
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the same thing, but included in the SystemVerilog definition.</p>
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</section>
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<section id="simtime">
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<h3><code class="docutils literal notranslate"><span class="pre">$simtime()</span></code><a class="headerlink" href="#simtime" title="Link to this heading">¶</a></h3>
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<p>This returns as a 64bit value the simulation time, unscaled by the time units
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of the local scope. This is different from the <code class="docutils literal notranslate"><span class="pre">$time</span></code> and <code class="docutils literal notranslate"><span class="pre">$stime</span></code>
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functions which return the scaled times. This function is added for regression
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testing of the compiler and run time, but can be used by applications who
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really want the simulation time.</p>
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<p>Note that the simulation time can be confusing if there are lots of different
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<code class="docutils literal notranslate"><span class="pre">`timescales</span></code> within a design. It is not in general possible to predict
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what the simulation precision will turn out to be.</p>
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</section>
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<section id="mti-random-mti-dist-uniform">
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<h3><code class="docutils literal notranslate"><span class="pre">$mti_random()</span></code>, <code class="docutils literal notranslate"><span class="pre">$mti_dist_uniform</span></code><a class="headerlink" href="#mti-random-mti-dist-uniform" title="Link to this heading">¶</a></h3>
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<p>These functions are similar to the IEEE 1364 standard <code class="docutils literal notranslate"><span class="pre">$random</span></code> functions,
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but they use the Mersenne Twister (MT19937) algorithm. This is considered an
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excellent random number generator, but does not generate the same sequence as
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the standardized <code class="docutils literal notranslate"><span class="pre">$random</span></code>.</p>
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</section>
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</section>
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<section id="system-tasks">
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<h2>System Tasks<a class="headerlink" href="#system-tasks" title="Link to this heading">¶</a></h2>
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<section id="readmempath">
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<h3><code class="docutils literal notranslate"><span class="pre">$readmempath</span></code><a class="headerlink" href="#readmempath" title="Link to this heading">¶</a></h3>
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<p>The <code class="docutils literal notranslate"><span class="pre">$readmemb</span></code> and <code class="docutils literal notranslate"><span class="pre">$readmemh</span></code> system tasks read text files that contain
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data values to populate memories. Normally, those files are found in a current
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working directory. The <code class="docutils literal notranslate"><span class="pre">$readmempath()</span></code> system task can be used to create a
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search path for those files. For example:</p>
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<div class="highlight-verilog notranslate"><div class="highlight"><pre><span></span><span class="kt">reg</span><span class="w"> </span><span class="p">[</span><span class="mh">7</span><span class="o">:</span><span class="mh">0</span><span class="p">]</span><span class="w"> </span><span class="n">mem</span><span class="w"> </span><span class="p">[</span><span class="mh">0</span><span class="o">:</span><span class="mh">7</span><span class="p">];</span>
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<span class="k">initial</span><span class="w"> </span><span class="k">begin</span>
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<span class="w"> </span><span class="nb">$readmemh</span><span class="p">(</span><span class="s">"datafile.txt"</span><span class="p">,</span><span class="w"> </span><span class="n">mem</span><span class="p">);</span>
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<span class="k">end</span>
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</pre></div>
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</div>
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<p>This assumes that “datafile.txt” is in the current working directory where
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the <code class="docutils literal notranslate"><span class="pre">vvp</span></code> command is running. But with the <code class="docutils literal notranslate"><span class="pre">$readmempath</span></code>, one can specify
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a search path:</p>
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<div class="highlight-verilog notranslate"><div class="highlight"><pre><span></span><span class="kt">reg</span><span class="w"> </span><span class="p">[</span><span class="mh">7</span><span class="o">:</span><span class="mh">0</span><span class="p">]</span><span class="w"> </span><span class="n">mem</span><span class="w"> </span><span class="p">[</span><span class="mh">0</span><span class="o">:</span><span class="mh">7</span><span class="p">];</span>
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<span class="k">initial</span><span class="w"> </span><span class="k">begin</span>
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<span class="w"> </span><span class="n">$readmempath</span><span class="p">(</span><span class="s">".:alternative:/global/defaults"</span><span class="p">);</span>
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<span class="w"> </span><span class="nb">$readmemh</span><span class="p">(</span><span class="s">"datafile.txt"</span><span class="p">,</span><span class="w"> </span><span class="n">mem</span><span class="p">);</span>
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<span class="k">end</span>
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</pre></div>
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</div>
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<p>In this example, “datafile.txt” is searched for in each of the directories
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in the above list (separated by “:” characters). The first located instance
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is the one that is used. So for example, if “./datafile.txt” exists, then it
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is read instead of “/global/defaults/datafile.txt” even if the latter exists.</p>
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</section>
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<section id="finish-and-return-code">
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<h3><code class="docutils literal notranslate"><span class="pre">$finish_and_return(code)</span></code><a class="headerlink" href="#finish-and-return-code" title="Link to this heading">¶</a></h3>
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<p>This task operates the same as the <code class="docutils literal notranslate"><span class="pre">$finish</span></code> system task, but adds the
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feature of specifying an exit code for the interpreter. This can be useful in
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automated test environments to indicate whether the simulation finished with
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or without errors.</p>
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</section>
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</section>
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<section id="extended-verilog-data-types">
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<h2>Extended Verilog Data Types<a class="headerlink" href="#extended-verilog-data-types" title="Link to this heading">¶</a></h2>
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<p>This feature is turned on by the generation flag “-gxtypes” and turned
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off by the generation flag “-gno-xtypes”. It is turned on by default.</p>
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<p>Icarus Verilog adds support for extended data types. This extended
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type syntax is based on a proposal by Cadence Design Systems,
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originally as an update to the IEEE 1364 standard. Icarus Verilog
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currently only takes the new primitive types from the proposal.</p>
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<p>SystemVerilog provides the same functionality using somewhat different
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syntax. This extension is maintained for backwards compatibility.</p>
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<ul class="simple">
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<li><p>Types</p></li>
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</ul>
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<p>Extended data types separates the concept of net/variable from the
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data type. Both nets and variables can declared with any data
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type. The primitive types available are:</p>
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<div class="highlight-none notranslate"><div class="highlight"><pre><span></span>logic - The familiar 0, 1, x and z, optionally with strength.
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bool - Limited to only 0 and 1
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real - 64-bit real values
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</pre></div>
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</div>
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<p>Nets with logic type may have multiple drivers with strength, and the
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value is resolved the usual way. Only logic values may be driven to
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logic nets, so bool values driven onto logic nets are implicitly
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converted to logic.</p>
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<p>Nets with any other type may not have multiple drivers. The compiler
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should detect the multiple drivers and report an error.</p>
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<ul class="simple">
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<li><p>Declarations</p></li>
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</ul>
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<p>The declaration of a net is extended to include the type of the wire,
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with the syntax:</p>
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<div class="highlight-none notranslate"><div class="highlight"><pre><span></span>wire <type> <wire-assignment-list>... ;
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</pre></div>
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</div>
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<p>The <type>, if omitted, is taken to be logic. The “wire” can be any of
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the net keywords. Wires can be logic, bool, real, or vectors of logic
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or bool. Some valid examples:</p>
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<div class="highlight-none notranslate"><div class="highlight"><pre><span></span>wire real foo = 1.0;
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tri logic bus[31:0];
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wire bool addr[23:0];
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... and so on.
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</pre></div>
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</div>
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<p>The declarations of variables is similar. The “reg” keyword is used to
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specify that this is a variable. Variables can have the same data
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types as nets.</p>
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<ul class="simple">
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<li><p>Ports</p></li>
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</ul>
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<p>Module and task ports in standard Verilog are restricted to logic
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types. This extension removes that restriction, allowing any of
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the above types to pass through the port consistent with the
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continuous assignment connectivity that is implied by the type.</p>
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<ul class="simple">
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<li><p>Expressions</p></li>
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</ul>
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<p>Expressions in the face of real values is covered by the baseline
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Verilog standard.</p>
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<p>The bool type supports the same operators as the logic type, with the
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obvious differences imposed by the limited domain.</p>
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<p>Comparison operators (not case compare) return logic if either of
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their operands is logic. If both are bool or real (including mix of
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bool and real) then the result is bool. This is because comparison of
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bools and reals always return exactly true or false.</p>
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<p>Case comparison returns bool. This differs from baseline Verilog,
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which strictly speaking returns a logic, but only 0 or 1 values.</p>
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<p>Arithmetic operators return real if either of their operands is real,
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otherwise they return logic if either of their operands is logic. If
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both operands are bool, they return bool.</p>
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</section>
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</section>
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</div>
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</div>
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</div>
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<div class="sphinxsidebar" role="navigation" aria-label="main navigation">
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<div class="sphinxsidebarwrapper">
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<h1 class="logo"><a href="../index.html">Icarus Verilog</a></h1>
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<h3>Navigation</h3>
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<p class="caption" role="heading"><span class="caption-text">Contents:</span></p>
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<ul class="current">
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<li class="toctree-l1 current"><a class="reference internal" href="index.html">Icarus Verilog Usage</a><ul class="current">
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<li class="toctree-l2"><a class="reference internal" href="installation.html">Installation Guide</a></li>
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<li class="toctree-l2"><a class="reference internal" href="getting_started.html">Getting Started With Icarus Verilog</a></li>
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<li class="toctree-l2"><a class="reference internal" href="simulation.html">Simulation Using Icarus Verilog</a></li>
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<li class="toctree-l2"><a class="reference internal" href="command_line_flags.html">iverilog Command Line Flags</a></li>
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<li class="toctree-l2"><a class="reference internal" href="command_files.html">Command File Format</a></li>
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<li class="toctree-l2"><a class="reference internal" href="verilog_attributes.html">Verilog Attributes</a></li>
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<li class="toctree-l2"><a class="reference internal" href="ivlpp_flags.html">IVLPP - IVL Preprocessor</a></li>
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<li class="toctree-l2"><a class="reference internal" href="vvp_flags.html">VVP Command Line Flags</a></li>
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<li class="toctree-l2"><a class="reference internal" href="vvp_debug.html">VVP Interactive Mode</a></li>
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<li class="toctree-l2"><a class="reference internal" href="vvp_library.html">VVP as a library</a></li>
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<li class="toctree-l2"><a class="reference internal" href="vhdlpp_flags.html">vhdlpp Command Line Flags</a></li>
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<li class="toctree-l2"><a class="reference internal" href="gtkwave.html">Waveforms With GTKWave</a></li>
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<li class="toctree-l2"><a class="reference internal" href="vpi.html">Using VPI</a></li>
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<li class="toctree-l2 current"><a class="current reference internal" href="#">Icarus Verilog Extensions</a></li>
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<li class="toctree-l2"><a class="reference internal" href="icarus_verilog_quirks.html">Icarus Verilog Quirks</a></li>
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<li class="toctree-l2"><a class="reference internal" href="reporting_issues.html">Reporting Issues</a></li>
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</ul>
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</li>
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<li class="toctree-l1"><a class="reference internal" href="../targets/index.html">The Icarus Verilog Targets</a></li>
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<li class="toctree-l1"><a class="reference internal" href="../developer/index.html">Icarus Verilog Developer Support</a></li>
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</ul>
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<div class="relations">
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<h3>Related Topics</h3>
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<ul>
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<li><a href="../index.html">Documentation overview</a><ul>
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<li><a href="index.html">Icarus Verilog Usage</a><ul>
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<li>Previous: <a href="vpi.html" title="previous chapter">Using VPI</a></li>
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<li>Next: <a href="icarus_verilog_quirks.html" title="next chapter">Icarus Verilog Quirks</a></li>
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</ul></li>
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</ul></li>
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</ul>
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</div>
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<div id="searchbox" style="display: none" role="search">
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<h3 id="searchlabel">Quick search</h3>
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<form class="search" action="../search.html" method="get">
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