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<title>Icarus Verilog Attributes — Icarus Verilog documentation</title>
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<div class="body" role="main">
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<section id="icarus-verilog-attributes">
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<h1>Icarus Verilog Attributes<a class="headerlink" href="#icarus-verilog-attributes" title="Link to this heading">¶</a></h1>
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<section id="attribute-naming-conventions">
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<h2>Attribute Naming Conventions<a class="headerlink" href="#attribute-naming-conventions" title="Link to this heading">¶</a></h2>
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<p>Attributes that are specific to Icarus Verilog, and are intended to be
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of use to programmers, start with the prefix “ivl_”.</p>
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<p>Attributes with the “_ivl_” prefix are set aside for internal
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use. They may be generated internally by the compiler. They need not
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be documented here.</p>
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</section>
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<section id="attributes-to-control-synthesis">
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<h2>Attributes To Control Synthesis<a class="headerlink" href="#attributes-to-control-synthesis" title="Link to this heading">¶</a></h2>
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<p>The following is a summary of Verilog attributes that Icarus Verilog
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understands within Verilog source files to control synthesis
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behavior. This section documents generic synthesis attributes. For
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target specific attributes, see target specific documentation.</p>
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<p>These attributes only effect the behavior of the synthesizer. For
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example, the ivl_combinational will not generate an error message
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if the Verilog is being compiled for simulation. (It may generate a
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warning.)</p>
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<ul class="simple">
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<li><p>Attributes for “always” and “initial” statements</p></li>
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</ul>
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<p>(* ivl_combinational *)</p>
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<blockquote>
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<div><p>This attribute tells the compiler that the statement models
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combinational logic. If the compiler finds that it cannot make
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combinational logic out of a marked always statement, it will
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report an error.</p>
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<p>This attribute can be used to prevent accidentally inferring
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latches or flip-flops where the user intended combinational
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logic.</p>
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</div></blockquote>
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<p>(* ivl_synthesis_on *)</p>
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<blockquote>
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<div><p>This attribute tells the compiler that the marked always statement
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is synthesizable. The compiler will attempt to synthesize the
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code in the marked “always” statement. If it cannot in any way
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synthesize it, then it will report an error.</p>
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</div></blockquote>
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<p>(* ivl_synthesis_off *)</p>
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<blockquote>
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<div><p>If this value is attached to an “always” statement, then the
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compiler will <em>not</em> synthesize the “always” statement. This can be
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used, for example, to mark embedded test bench code.</p>
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</div></blockquote>
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<ul class="simple">
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<li><p>Attributes for modules</p></li>
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</ul>
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<p>(* ivl_synthesis_cell *)</p>
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<blockquote>
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<div><p>If this value is attached to a module during synthesis, that
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module will be considered a target architecture primitive, and
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its interior will not be synthesized further. The module can
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therefore hold a model for simulation purposes.</p>
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</div></blockquote>
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<ul class="simple">
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<li><p>Attributes for signals (wire/reg/integer/tri/etc.)</p></li>
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</ul>
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<p>(* PAD = “<pad assignment list>” *)</p>
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<blockquote>
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<div><p>If this attribute is attached to a signal that happens to be a
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root module port, then targets that support it will use the string
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value as a list of pin assignments for the port/signal. The format
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is a comma separated list of location tokens, with the format of
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the token itself defined by the back-end tools in use.</p>
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</div></blockquote>
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<ul class="simple">
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<li><p>Other Attributes</p></li>
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</ul>
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<p>[ none defined yet ]</p>
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</section>
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<section id="misc">
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<h2>Misc<a class="headerlink" href="#misc" title="Link to this heading">¶</a></h2>
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<p>(* _ivl_schedule_push *)</p>
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<blockquote>
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<div><p>If this attribute is attached to a thread object (always or
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initial statement) then the vvp code generator will generate code
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that causes the scheduler to push this thread at compile time. The
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compiler may internally add this attribute to always statements if
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it detects that it is combinational. This helps resolve time-0
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races.</p>
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</div></blockquote>
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</section>
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</section>
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