50 lines
1.5 KiB
Plaintext
50 lines
1.5 KiB
Plaintext
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ATTRIBUTES TO CONTROL SYNTHESIS
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The following is a summary of Verilog attributes that Icarus Verilog
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understands within Verilog source files to control synthesis
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behavior. This section documents generic synthesis attributes. For
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target specific attributes, see target specific documentation.
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These attributes only effect the behavior of the synthesizer. For
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example, the ivl_combinational will not generate an error message
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if the Verilog is being compiled for simulation. (It may generate a
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warning.)
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* Attributes for "always" and "initial" statements
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(* ivl_combinational *)
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This attribute tells the compiler that the statement models
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combinational logic. If the compiler finds that it cannot make
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combinational logic out of a marked always statement, it will
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report an error.
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This attribute can be used to prevent accidentally inferring
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latches or flip-flops where the user intended combinational
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logic.
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(* ivl_synthesis_on *)
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This attribute tells the compiler that the marked always statement
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is synthesizeable. The compiler will attempt to synthesize the
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code in the marked "always" statement. If it cannot in any way
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synthesize it, then it will report an error.
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(* ivl_synthesis_off *)
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If this value is attached to an "always" statement, then the
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compiler will *not* synthesize the "always" statment. This can be
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used, for example, to mark embedded test bench code.
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* Attributes for signals (wire/reg/integer/tri/etc.)
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[ none defined yet ]
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* Other Attributes
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[ none defined yet ]
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