14 lines
244 B
Coq
14 lines
244 B
Coq
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// Check that a SystemVerilog do/while loop works correctly.
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module top;
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int i;
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initial begin
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i = 0;
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do begin
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i += 1;
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$display("The value of i is %0d", i);
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end while (i < 2);
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$display("PASSED");
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end
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endmodule
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