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<div class="body" role="main">
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<section id="simulation-using-icarus-verilog">
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<h1>Simulation Using Icarus Verilog<a class="headerlink" href="#simulation-using-icarus-verilog" title="Link to this heading">¶</a></h1>
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<p>Simulation is the process of creating models that mimic the behavior of the
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device you are designing (simulation models) and creating models to exercise
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the device (test benches). The simulation model need not reflect any
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understanding of the underlying technology, and the simulator need not know
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that the design is intended for any specific technology.</p>
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<p>The Verilog simulator, in fact, is usually a different program than the
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synthesizer. It may even come from a different vendor. The simulator need not
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know of or generate netlists for the target technology, so it is possible to
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write one simulator that can be used to model designs intended for a wide
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variety of technologies. A synthesizer, on the other hand, does need to know a
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great deal about the target technology in order to generate efficient
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netlists. Synthesizers are often technology specific and come from vendors
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with specialized knowledge, whereas simulators are more general purpose.</p>
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<p>Simulation models and test benches, therefore, can use the full range of
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Verilog features to model the intended design as clearly as possible. This is
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the time to test the algorithms of the design using language that is
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relatively easy for humans to read. The simulator, along with the test bench,
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can test that the clearly written model really does behave as intended, and
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that the intended behavior really does meet expectations.</p>
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<p>The test benches model the world outside the design, so they are rarely
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destined for real hardware. They are written in Verilog simply as a matter of
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convenience, and sometimes they are not written in Verilog at all. The test
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benches are not throw-away code either, as they are used to retest the device
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under test as it is transformed from a simulation model to a synthesizeable
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description.</p>
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<section id="compilation-and-elaboration">
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<h2>Compilation and Elaboration<a class="headerlink" href="#compilation-and-elaboration" title="Link to this heading">¶</a></h2>
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<p>Simulation of a design amounts to compiling and executing a program. The
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Verilog source that represents the simulation model and the test bench is
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compiled into an executable form and executed by a simulation
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engine. Internally, Icarus Verilog divides the compilation of program source
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to an executable form into several steps, and basic understanding of these
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steps helps understand the nature of failures and errors. The first step is
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macro preprocessing, then compilation, elaboration, optional optimizations and
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finally code generation. The boundary between these steps is often blurred,
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but this progression remains a useful model of the compilation process.</p>
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<p>The macro preprocessing step performs textual substitutions of macros defined
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with “`define” statements, textual inclusion with “`include” statements, and
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conditional compilation by “`ifdef” and “`ifndef” statements. The
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macropreprocessor for Icarus Verilog is internally a separate program that can
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be accessed independently by using the “-E” flag to the “iverilog” command,
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like so:</p>
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<div class="highlight-none notranslate"><div class="highlight"><pre><span></span>% iverilog -E -o out.v example.v
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</pre></div>
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</div>
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<p>This command causes the input Verilog file “example.v” to be preprocessed, and
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the output, a Verilog file without preprocessor statements, written into
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“out.v”. The “`include” and “`ifdef” directives in the input file are interpreted,
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and defined macros substituted, so that the output, a single file, is the same
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Verilog but with the preprocessor directives gone. All the explicitly
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specified source files are also combined by the preprocessor, so that the
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preprocessed result is a single Verilog stream.</p>
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<p>Normally, however, the “-E” flag is not used and the preprocessed Verilog is
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instead sent directly to the next step, the compiler. The compiler core takes
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as input preprocessed Verilog and generates an internal parsed form. The
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parsed form is an internal representation of the Verilog source, in a format
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convenient for further processing, and is not accessible to the user.</p>
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<p>The next step, elaboration, takes the parsed form, chooses the root modules,
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and instantiates (makes <em>instances</em> of) those roots. The root instances may
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contain instances of other modules, which may in turn contain instances of yet
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other modules. The elaboration process creates a hierarchy of module instances
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that ends with primitive gates and statements.</p>
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<p>Note that there is a difference between a module and a module instance. A
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module is a type. It is a description of the contents of module instances that
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have its type. When a module is instantiated within another module, the module
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name identifies the type of the instance, and the instance name identifies the
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specific instance of the module. There can be many instances of any given
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module.</p>
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<p>Root modules are a special case, in that the programmer does not give them
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instance names. Instead, the instance names of root modules are the same as
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the name of the module. This is valid because, due to the nature of the
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Verilog syntax, a module can be a root module only once, so the module name
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itself is a safe instance name.</p>
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<p>Elaboration creates a hierarchy of scopes. Each module instance creates a new
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scope within its parent module, with each root module starting a
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hierarchy. Every module instance in the elaborated program has a unique scope
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path, a hierarchical name, that starts with its root scope and ends with its
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own instance name. Every named object, including variables, parameters, nets
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and gates, also has a hierarchical name that starts with a root scope and ends
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with its own base name. The compiler uses hierarchical names in error messages
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generated during or after elaboration, so that erroneous items can be
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completely identified. These hierarchical names are also used by waveform
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viewers that display waveform output from simulations.</p>
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<p>The elaboration process creates from the parsed form the scope hierarchy
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including the primitive objects within each scope. The elaborated design then
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is optimized to reduce it to a more optimal, but equivalent design. The
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optimization step takes the fully elaborated design and transforms it to an
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equivalent design that is smaller or more efficient. These optimizations are,
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for example, forms of constant propagation and dead code elimination. Useless
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logic is eliminated, and constant expressions are pre-calculated. The
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resulting design behaves as if the optimizations were not performed, but is
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smaller and more efficient. The elimination (and spontaneous creation) of
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gates and statements only affects the programmer when writing VPI modules,
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which through the API have limited access to the structures of the design.</p>
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<p>Finally, the optimized design, which is still in an internal form not
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accessible to users, is passed to a code generator that writes the design into
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an executable form. For simulation, the code generator is selected to generate
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the vvp format–a text format that can be executed by the simulation
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engine. Other code generators may be selected by the Icarus Verilog user, even
|
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third party code generators, but the vvp code generator is the default for
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simulation purposes.</p>
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</section>
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<section id="making-and-using-libraries">
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<h2>Making and Using Libraries<a class="headerlink" href="#making-and-using-libraries" title="Link to this heading">¶</a></h2>
|
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<p>Although simple programs may be written into a single source file, this gets
|
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inconvenient as the designs get larger. Also, writing the entire program into
|
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a single file makes it difficult for different programs to share common
|
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|
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code. It therefore makes sense to divide large programs into several source
|
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files, and to put generally useful source code files somewhere accessible to
|
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multiple designs.</p>
|
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<p>Once the program is divided into many files, the compiler needs to be told how
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to find the files of the program. The simplest way to do that is to list the
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source files on the command line or in a command file. This is for example the
|
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best way to divide up and integrate test bench code with the simulation model
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of the device under test.</p>
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<section id="the-macro-preprocessor">
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<h3>The Macro Preprocessor<a class="headerlink" href="#the-macro-preprocessor" title="Link to this heading">¶</a></h3>
|
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<p>Another technique is to use the macro preprocessor to include library files
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into a main file. The <cite>include</cite> directive takes the name of a source file to
|
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include. The preprocessor inserts the entire contents of the included file in
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place of the <cite>include</cite> directive. The preprocessor normally looks in the
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current working directory (the current working directory of the running
|
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compiler, and not the directory where the source file is located) for the
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included file, but the “-I” switch to “iverilog” can add directories to the
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search locations list.</p>
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<div class="highlight-none notranslate"><div class="highlight"><pre><span></span>% iverilog -I/directory/to/search example.v
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</pre></div>
|
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</div>
|
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<p>It is common to create include directories shared by a set of programs. The
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preprocessor <cite>include</cite> directive can be used by the individual programs to
|
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include the source files that it needs.</p>
|
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<p>The preprocessor method of placing source code into libraries is general
|
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(arbitrary source code can be placed in the included files) but is static, in
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the sense that the programmer must explicitly include the desired library
|
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files. The automatic module library is a bit more constrained, but is
|
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automatic.</p>
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</section>
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<section id="automatic-module-libraries">
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<h3>Automatic Module Libraries<a class="headerlink" href="#automatic-module-libraries" title="Link to this heading">¶</a></h3>
|
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<p>A common use for libraries is to store module definitions that may be of use
|
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to a variety of programs. If modules are divided into a single module per
|
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file, and the files are named appropriately, and the compiler is told where to
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look, then the compiler can automatically locate library files when it finds
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that a module definition is missing.</p>
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<p>For this to work properly, the library files must be Verilog source, they
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should contain a single module definition, and the files must be named after
|
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the module they contain. For example, if the module “AND2” is a module in the
|
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library, then it belongs in a file called “AND2.v” and that file contains only
|
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the “AND2” module. A library, then, is a directory that contains properly
|
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named and formatted source files.</p>
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<div class="highlight-none notranslate"><div class="highlight"><pre><span></span>% iverilog -y/library/to/search example.v
|
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</pre></div>
|
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</div>
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<p>The “-y” flag to “iverilog” tells the compiler to look in the specified
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directory for library modules whenever the program instantiates a module that
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is not otherwise defined. The programmer may include several “-y” flags on the
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command line (or in a command file) and the compiler will search each
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directory in order until an appropriate library file is found to resolve the
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module.</p>
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<p>Once a module is defined, either in the program or by reading a library
|
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module, the loaded definition is used from then on within the program. If the
|
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module is defined within a program file or within an included file, then the
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included definition is used instead of any library definition. If a module is
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defined in multiple libraries, then the first definition that the compiler
|
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finds is used, and later definitions are never read.</p>
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<p>Icarus Verilog accesses automatic libraries during elaboration, after it has
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already preprocessed and parsed the non-library source files. Modules in
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libraries are not candidates for root modules, and are not even parsed unless
|
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they are instantiated in other source files. However, a library module may
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reference other library modules, and reading in a library module causes it to
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be parsed and elaborated, and further library references resolved, just like a
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non-library module. The library lookup and resolution process iterates until
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all referenced modules are resolved, or known to be missing from the
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libraries.</p>
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<p>The automatic module library technique is useful for including vendor or
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technology libraries into a program. Many EDA vendors offer module libraries
|
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that are formatted appropriately; and with this technique, Icarus Verilog can
|
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use them for simulation.</p>
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</section>
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</section>
|
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<section id="advanced-command-files">
|
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<h2>Advanced Command Files<a class="headerlink" href="#advanced-command-files" title="Link to this heading">¶</a></h2>
|
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<p>Command files were mentioned in the “Getting Started” chapter, but only
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briefly. In practice, Verilog programs quickly grow far beyond the usefulness
|
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of simple command line options, and even the macro preprocessor lacks the
|
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flexibility to combine source and library modules according to the advancing
|
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development process.</p>
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<p>The main contents of a command file is a list of Verilog source files. You can
|
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name in a command file all the source files that make up your design. This is
|
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a convenient way to collect together all the files that make up your
|
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design. Compiling the design can then be reduced to a simple command line like
|
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the following:</p>
|
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<div class="highlight-none notranslate"><div class="highlight"><pre><span></span>% iverilog -c example.cf
|
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</pre></div>
|
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</div>
|
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<p>The command file describes a configuration. That is, it lists the specific
|
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files that make up your design. It is reasonable, during the course of
|
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development, to have a set of different but similar variations of your
|
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|
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design. These variations may have different source files but also many common
|
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|
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source files. A command file can be written for each variation, and each
|
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command file lists the source file names used by each variation.</p>
|
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<p>A configuration may also specify the use of libraries. For example, different
|
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configurations may be implementations for different technologies so may use
|
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|
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different parts libraries. To make this work, command files may include “-y”
|
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statements. These work in command files exactly how they work on “iverilog”
|
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command line. Each “-y” flag is followed by a directory name, and the
|
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directories are searched for library modules in the order that they are listed
|
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in the command file.</p>
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<p>The include search path can also be specified in configuration files with
|
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“+incdir+” tokens. These tokens start with the “+incdir+” string, then
|
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continue with directory paths, separated from each other with “+” characters
|
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(not spaces) for the length of the line.</p>
|
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<p>Other information can be included in the command file. See the section Command
|
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File Format for complete details on what can go in a command file.</p>
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|
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</section>
|
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|
|
<section id="input-data-at-runtime">
|
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|
|
<h2>Input Data at Runtime<a class="headerlink" href="#input-data-at-runtime" title="Link to this heading">¶</a></h2>
|
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|
|
<p>Often, it is useful to compile a program into an executable simulation, then
|
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|
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run the simulation with various inputs. This requires some means to pass data
|
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|
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and arguments to the compiled program each time it is executed. For example,
|
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if the design models a micro-controller, one would like to run the compiled
|
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simulation against a variety of different ROM images.</p>
|
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<p>There are a variety of ways for a Verilog program to get data from the outside
|
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world into the program at run time. Arguments can be entered on the command
|
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line, and larger amounts of data can be read from files. The simplest method
|
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is to take arguments from the command line.</p>
|
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<p>Consider this running example of a square root calculator</p>
|
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|
|
<div class="highlight-verilog notranslate"><div class="highlight"><pre><span></span><span class="k">module</span><span class="w"> </span><span class="n">sqrt32</span><span class="p">(</span><span class="n">clk</span><span class="p">,</span><span class="w"> </span><span class="n">rdy</span><span class="p">,</span><span class="w"> </span><span class="n">reset</span><span class="p">,</span><span class="w"> </span><span class="n">x</span><span class="p">,</span><span class="w"> </span><span class="p">.</span><span class="n">y</span><span class="p">(</span><span class="n">acc</span><span class="p">));</span>
|
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|
|
<span class="w"> </span><span class="k">input</span><span class="w"> </span><span class="n">clk</span><span class="p">;</span>
|
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|
<span class="w"> </span><span class="k">output</span><span class="w"> </span><span class="n">rdy</span><span class="p">;</span>
|
|||
|
|
<span class="w"> </span><span class="k">input</span><span class="w"> </span><span class="n">reset</span><span class="p">;</span>
|
|||
|
|
|
|||
|
|
<span class="w"> </span><span class="k">input</span><span class="w"> </span><span class="p">[</span><span class="mh">31</span><span class="o">:</span><span class="mh">0</span><span class="p">]</span><span class="w"> </span><span class="n">x</span><span class="p">;</span>
|
|||
|
|
<span class="w"> </span><span class="k">output</span><span class="w"> </span><span class="p">[</span><span class="mh">15</span><span class="o">:</span><span class="mh">0</span><span class="p">]</span><span class="w"> </span><span class="n">acc</span><span class="p">;</span>
|
|||
|
|
|
|||
|
|
<span class="w"> </span><span class="c1">// acc holds the accumulated result, and acc2 is</span>
|
|||
|
|
<span class="w"> </span><span class="c1">// the accumulated square of the accumulated result.</span>
|
|||
|
|
<span class="w"> </span><span class="kt">reg</span><span class="w"> </span><span class="p">[</span><span class="mh">15</span><span class="o">:</span><span class="mh">0</span><span class="p">]</span><span class="w"> </span><span class="n">acc</span><span class="p">;</span>
|
|||
|
|
<span class="w"> </span><span class="kt">reg</span><span class="w"> </span><span class="p">[</span><span class="mh">31</span><span class="o">:</span><span class="mh">0</span><span class="p">]</span><span class="w"> </span><span class="n">acc2</span><span class="p">;</span>
|
|||
|
|
|
|||
|
|
<span class="w"> </span><span class="c1">// Keep track of which bit I'm working on.</span>
|
|||
|
|
<span class="w"> </span><span class="kt">reg</span><span class="w"> </span><span class="p">[</span><span class="mh">4</span><span class="o">:</span><span class="mh">0</span><span class="p">]</span><span class="w"> </span><span class="n">bitl</span><span class="p">;</span>
|
|||
|
|
<span class="w"> </span><span class="kt">wire</span><span class="w"> </span><span class="p">[</span><span class="mh">15</span><span class="o">:</span><span class="mh">0</span><span class="p">]</span><span class="w"> </span><span class="kt">bit</span><span class="w"> </span><span class="o">=</span><span class="w"> </span><span class="mh">1</span><span class="w"> </span><span class="o"><<</span><span class="w"> </span><span class="n">bitl</span><span class="p">;</span>
|
|||
|
|
<span class="w"> </span><span class="kt">wire</span><span class="w"> </span><span class="p">[</span><span class="mh">31</span><span class="o">:</span><span class="mh">0</span><span class="p">]</span><span class="w"> </span><span class="n">bit2</span><span class="w"> </span><span class="o">=</span><span class="w"> </span><span class="mh">1</span><span class="w"> </span><span class="o"><<</span><span class="w"> </span><span class="p">(</span><span class="n">bitl</span><span class="w"> </span><span class="o"><<</span><span class="w"> </span><span class="mh">1</span><span class="p">);</span>
|
|||
|
|
|
|||
|
|
<span class="w"> </span><span class="c1">// The output is ready when the bitl counter underflows.</span>
|
|||
|
|
<span class="w"> </span><span class="kt">wire</span><span class="w"> </span><span class="n">rdy</span><span class="w"> </span><span class="o">=</span><span class="w"> </span><span class="n">bitl</span><span class="p">[</span><span class="mh">4</span><span class="p">];</span>
|
|||
|
|
|
|||
|
|
<span class="w"> </span><span class="c1">// guess holds the potential next values for acc,</span>
|
|||
|
|
<span class="w"> </span><span class="c1">// and guess2 holds the square of that guess.</span>
|
|||
|
|
<span class="w"> </span><span class="kt">wire</span><span class="w"> </span><span class="p">[</span><span class="mh">15</span><span class="o">:</span><span class="mh">0</span><span class="p">]</span><span class="w"> </span><span class="n">guess</span><span class="w"> </span><span class="o">=</span><span class="w"> </span><span class="n">acc</span><span class="w"> </span><span class="o">|</span><span class="w"> </span><span class="kt">bit</span><span class="p">;</span>
|
|||
|
|
<span class="w"> </span><span class="kt">wire</span><span class="w"> </span><span class="p">[</span><span class="mh">31</span><span class="o">:</span><span class="mh">0</span><span class="p">]</span><span class="w"> </span><span class="n">guess2</span><span class="w"> </span><span class="o">=</span><span class="w"> </span><span class="n">acc2</span><span class="w"> </span><span class="o">+</span><span class="w"> </span><span class="n">bit2</span><span class="w"> </span><span class="o">+</span><span class="w"> </span><span class="p">((</span><span class="n">acc</span><span class="w"> </span><span class="o"><<</span><span class="w"> </span><span class="n">bitl</span><span class="p">)</span><span class="w"> </span><span class="o"><<</span><span class="w"> </span><span class="mh">1</span><span class="p">);</span>
|
|||
|
|
|
|||
|
|
<span class="w"> </span><span class="k">task</span><span class="w"> </span><span class="n">clear</span><span class="p">;</span>
|
|||
|
|
<span class="w"> </span><span class="k">begin</span>
|
|||
|
|
<span class="w"> </span><span class="n">acc</span><span class="w"> </span><span class="o">=</span><span class="w"> </span><span class="mh">0</span><span class="p">;</span>
|
|||
|
|
<span class="w"> </span><span class="n">acc2</span><span class="w"> </span><span class="o">=</span><span class="w"> </span><span class="mh">0</span><span class="p">;</span>
|
|||
|
|
<span class="w"> </span><span class="n">bitl</span><span class="w"> </span><span class="o">=</span><span class="w"> </span><span class="mh">15</span><span class="p">;</span>
|
|||
|
|
<span class="w"> </span><span class="k">end</span>
|
|||
|
|
<span class="w"> </span><span class="k">endtask</span>
|
|||
|
|
|
|||
|
|
<span class="w"> </span><span class="k">initial</span><span class="w"> </span><span class="n">clear</span><span class="p">;</span>
|
|||
|
|
|
|||
|
|
<span class="w"> </span><span class="k">always</span><span class="w"> </span><span class="p">@(</span><span class="n">reset</span><span class="w"> </span><span class="k">or</span><span class="w"> </span><span class="k">posedge</span><span class="w"> </span><span class="n">clk</span><span class="p">)</span>
|
|||
|
|
<span class="w"> </span><span class="k">if</span><span class="w"> </span><span class="p">(</span><span class="n">reset</span><span class="p">)</span>
|
|||
|
|
<span class="w"> </span><span class="n">clear</span><span class="p">;</span>
|
|||
|
|
<span class="w"> </span><span class="k">else</span><span class="w"> </span><span class="k">begin</span>
|
|||
|
|
<span class="w"> </span><span class="k">if</span><span class="w"> </span><span class="p">(</span><span class="n">guess2</span><span class="w"> </span><span class="o"><=</span><span class="w"> </span><span class="n">x</span><span class="p">)</span><span class="w"> </span><span class="k">begin</span>
|
|||
|
|
<span class="w"> </span><span class="n">acc</span><span class="w"> </span><span class="o"><=</span><span class="w"> </span><span class="n">guess</span><span class="p">;</span>
|
|||
|
|
<span class="w"> </span><span class="n">acc2</span><span class="w"> </span><span class="o"><=</span><span class="w"> </span><span class="n">guess2</span><span class="p">;</span>
|
|||
|
|
<span class="w"> </span><span class="k">end</span>
|
|||
|
|
<span class="w"> </span><span class="n">bitl</span><span class="w"> </span><span class="o"><=</span><span class="w"> </span><span class="n">bitl</span><span class="w"> </span><span class="o">-</span><span class="w"> </span><span class="mh">1</span><span class="p">;</span>
|
|||
|
|
<span class="w"> </span><span class="k">end</span>
|
|||
|
|
|
|||
|
|
<span class="k">endmodule</span>
|
|||
|
|
</pre></div>
|
|||
|
|
</div>
|
|||
|
|
<p>One could write the test bench as a program that passes a representative set
|
|||
|
|
of input values into the device and checks the output result. However, we can
|
|||
|
|
also write a program that takes on the command line an integer value to be
|
|||
|
|
used as input to the device. We can write and compile this program, then pass
|
|||
|
|
different input values on the run time command line without recompiling the
|
|||
|
|
simulation.</p>
|
|||
|
|
<p>This example demonstrates the use of the “$value$plusargs” to access command
|
|||
|
|
line arguments of a simulation</p>
|
|||
|
|
<div class="highlight-verilog notranslate"><div class="highlight"><pre><span></span><span class="k">module</span><span class="w"> </span><span class="n">main</span><span class="p">;</span>
|
|||
|
|
|
|||
|
|
<span class="w"> </span><span class="kt">reg</span><span class="w"> </span><span class="n">clk</span><span class="p">,</span><span class="w"> </span><span class="n">reset</span><span class="p">;</span>
|
|||
|
|
<span class="w"> </span><span class="kt">reg</span><span class="w"> </span><span class="p">[</span><span class="mh">31</span><span class="o">:</span><span class="mh">0</span><span class="p">]</span><span class="w"> </span><span class="n">x</span><span class="p">;</span>
|
|||
|
|
<span class="w"> </span><span class="kt">wire</span><span class="w"> </span><span class="p">[</span><span class="mh">15</span><span class="o">:</span><span class="mh">0</span><span class="p">]</span><span class="w"> </span><span class="n">y</span><span class="p">;</span>
|
|||
|
|
<span class="w"> </span><span class="kt">wire</span><span class="w"> </span><span class="n">rdy</span><span class="p">;</span>
|
|||
|
|
|
|||
|
|
<span class="w"> </span><span class="n">sqrt32</span><span class="w"> </span><span class="n">dut</span><span class="w"> </span><span class="p">(</span><span class="n">clk</span><span class="p">,</span><span class="w"> </span><span class="n">rdy</span><span class="p">,</span><span class="w"> </span><span class="n">reset</span><span class="p">,</span><span class="w"> </span><span class="n">x</span><span class="p">,</span><span class="w"> </span><span class="n">y</span><span class="p">);</span>
|
|||
|
|
|
|||
|
|
<span class="w"> </span><span class="k">always</span><span class="w"> </span><span class="p">#</span><span class="mh">10</span><span class="w"> </span><span class="n">clk</span><span class="w"> </span><span class="o">=</span><span class="w"> </span><span class="o">~</span><span class="n">clk</span><span class="p">;</span>
|
|||
|
|
|
|||
|
|
<span class="w"> </span><span class="k">initial</span><span class="w"> </span><span class="k">begin</span>
|
|||
|
|
<span class="w"> </span><span class="n">clk</span><span class="w"> </span><span class="o">=</span><span class="w"> </span><span class="mh">0</span><span class="p">;</span>
|
|||
|
|
<span class="w"> </span><span class="n">reset</span><span class="w"> </span><span class="o">=</span><span class="w"> </span><span class="mh">1</span><span class="p">;</span>
|
|||
|
|
|
|||
|
|
<span class="w"> </span><span class="k">if</span><span class="w"> </span><span class="p">(</span><span class="o">!</span><span class="w"> </span><span class="n">$value$plusargs</span><span class="p">(</span><span class="s">"x=%d"</span><span class="p">,</span><span class="w"> </span><span class="n">x</span><span class="p">))</span><span class="w"> </span><span class="k">begin</span>
|
|||
|
|
<span class="w"> </span><span class="nb">$display</span><span class="p">(</span><span class="s">"ERROR: please specify +x=<value> to start."</span><span class="p">);</span>
|
|||
|
|
<span class="w"> </span><span class="nb">$finish</span><span class="p">;</span>
|
|||
|
|
<span class="w"> </span><span class="k">end</span>
|
|||
|
|
|
|||
|
|
<span class="w"> </span><span class="p">#</span><span class="mh">35</span><span class="w"> </span><span class="n">reset</span><span class="w"> </span><span class="o">=</span><span class="w"> </span><span class="mh">0</span><span class="p">;</span>
|
|||
|
|
|
|||
|
|
<span class="w"> </span><span class="k">wait</span><span class="w"> </span><span class="p">(</span><span class="n">rdy</span><span class="p">)</span><span class="w"> </span><span class="nb">$display</span><span class="p">(</span><span class="s">"y=%d"</span><span class="p">,</span><span class="w"> </span><span class="n">y</span><span class="p">);</span>
|
|||
|
|
<span class="w"> </span><span class="nb">$finish</span><span class="p">;</span>
|
|||
|
|
<span class="w"> </span><span class="k">end</span><span class="w"> </span><span class="c1">// initial begin</span>
|
|||
|
|
|
|||
|
|
<span class="k">endmodule</span><span class="w"> </span><span class="c1">// main</span>
|
|||
|
|
</pre></div>
|
|||
|
|
</div>
|
|||
|
|
<p>The “$value$plusargs” system function takes a string pattern that describes
|
|||
|
|
the format of the command line argument, and a reference to a variable that
|
|||
|
|
receives the value. The “sqrt_plusargs” program can be compiled and executed
|
|||
|
|
like this:</p>
|
|||
|
|
<div class="highlight-none notranslate"><div class="highlight"><pre><span></span>% iverilog -osqrt_plusargs.vvp sqrt_plusargs.v sqrt.v
|
|||
|
|
% vvp sqrt_plusargs.vvp +x=81
|
|||
|
|
y= 9
|
|||
|
|
</pre></div>
|
|||
|
|
</div>
|
|||
|
|
<p>Notice that the “x=%d” string of the “$value$plusargs” function describes the
|
|||
|
|
format of the argument. The “%d” matches a decimal value, which in the sample
|
|||
|
|
run is “81”. This gets assigned to “x” by the “$value$plusargs” function,
|
|||
|
|
which returns TRUE, and the simulation continues from there.</p>
|
|||
|
|
<p>If two arguments have to be passed to the testbench then the main module would
|
|||
|
|
be modified as follows</p>
|
|||
|
|
<div class="highlight-verilog notranslate"><div class="highlight"><pre><span></span><span class="k">module</span><span class="w"> </span><span class="n">main</span><span class="p">;</span>
|
|||
|
|
|
|||
|
|
<span class="w"> </span><span class="kt">reg</span><span class="w"> </span><span class="n">clk</span><span class="p">,</span><span class="w"> </span><span class="n">reset</span><span class="p">;</span>
|
|||
|
|
<span class="w"> </span><span class="kt">reg</span><span class="w"> </span><span class="p">[</span><span class="mh">31</span><span class="o">:</span><span class="mh">0</span><span class="p">]</span><span class="w"> </span><span class="n">x</span><span class="p">;</span>
|
|||
|
|
<span class="w"> </span><span class="kt">reg</span><span class="w"> </span><span class="p">[</span><span class="mh">31</span><span class="o">:</span><span class="mh">0</span><span class="p">]</span><span class="w"> </span><span class="n">z</span><span class="p">;</span>
|
|||
|
|
<span class="w"> </span><span class="kt">wire</span><span class="w"> </span><span class="p">[</span><span class="mh">15</span><span class="o">:</span><span class="mh">0</span><span class="p">]</span><span class="w"> </span><span class="n">y1</span><span class="p">,</span><span class="n">y2</span><span class="p">;</span>
|
|||
|
|
<span class="w"> </span><span class="kt">wire</span><span class="w"> </span><span class="n">rdy1</span><span class="p">,</span><span class="n">rdy2</span><span class="p">;</span>
|
|||
|
|
|
|||
|
|
<span class="w"> </span><span class="n">sqrt32</span><span class="w"> </span><span class="n">dut1</span><span class="w"> </span><span class="p">(</span><span class="n">clk</span><span class="p">,</span><span class="w"> </span><span class="n">rdy1</span><span class="p">,</span><span class="w"> </span><span class="n">reset</span><span class="p">,</span><span class="w"> </span><span class="n">x</span><span class="p">,</span><span class="w"> </span><span class="n">y1</span><span class="p">);</span>
|
|||
|
|
<span class="w"> </span><span class="n">sqrt32</span><span class="w"> </span><span class="n">dut2</span><span class="w"> </span><span class="p">(</span><span class="n">clk</span><span class="p">,</span><span class="w"> </span><span class="n">rdy2</span><span class="p">,</span><span class="w"> </span><span class="n">reset</span><span class="p">,</span><span class="w"> </span><span class="n">z</span><span class="p">,</span><span class="w"> </span><span class="n">y2</span><span class="p">);</span>
|
|||
|
|
|
|||
|
|
<span class="w"> </span><span class="k">always</span><span class="w"> </span><span class="p">#</span><span class="mh">10</span><span class="w"> </span><span class="n">clk</span><span class="w"> </span><span class="o">=</span><span class="w"> </span><span class="o">~</span><span class="n">clk</span><span class="p">;</span>
|
|||
|
|
|
|||
|
|
<span class="w"> </span><span class="k">initial</span><span class="w"> </span><span class="k">begin</span>
|
|||
|
|
<span class="w"> </span><span class="n">clk</span><span class="w"> </span><span class="o">=</span><span class="w"> </span><span class="mh">0</span><span class="p">;</span>
|
|||
|
|
<span class="w"> </span><span class="n">reset</span><span class="w"> </span><span class="o">=</span><span class="w"> </span><span class="mh">1</span><span class="p">;</span>
|
|||
|
|
|
|||
|
|
<span class="w"> </span><span class="k">if</span><span class="w"> </span><span class="p">(</span><span class="o">!</span><span class="w"> </span><span class="n">$value$plusargs</span><span class="p">(</span><span class="s">"x=%d"</span><span class="p">,</span><span class="w"> </span><span class="n">x</span><span class="p">))</span><span class="w"> </span><span class="k">begin</span>
|
|||
|
|
<span class="w"> </span><span class="nb">$display</span><span class="p">(</span><span class="s">"ERROR: please specify +x=<value> to start."</span><span class="p">);</span>
|
|||
|
|
<span class="w"> </span><span class="nb">$finish</span><span class="p">;</span>
|
|||
|
|
<span class="w"> </span><span class="k">end</span>
|
|||
|
|
|
|||
|
|
<span class="w"> </span><span class="k">if</span><span class="w"> </span><span class="p">(</span><span class="o">!</span><span class="w"> </span><span class="n">$value$plusargs</span><span class="p">(</span><span class="s">"z=%d"</span><span class="p">,</span><span class="w"> </span><span class="n">z</span><span class="p">))</span><span class="w"> </span><span class="k">begin</span>
|
|||
|
|
<span class="w"> </span><span class="nb">$display</span><span class="p">(</span><span class="s">"ERROR: please specify +z=<value> to start."</span><span class="p">);</span>
|
|||
|
|
<span class="w"> </span><span class="nb">$finish</span><span class="p">;</span>
|
|||
|
|
<span class="w"> </span><span class="k">end</span>
|
|||
|
|
|
|||
|
|
|
|||
|
|
<span class="w"> </span><span class="p">#</span><span class="mh">35</span><span class="w"> </span><span class="n">reset</span><span class="w"> </span><span class="o">=</span><span class="w"> </span><span class="mh">0</span><span class="p">;</span>
|
|||
|
|
|
|||
|
|
<span class="w"> </span><span class="k">wait</span><span class="w"> </span><span class="p">(</span><span class="n">rdy1</span><span class="p">)</span><span class="w"> </span><span class="nb">$display</span><span class="p">(</span><span class="s">"y1=%d"</span><span class="p">,</span><span class="w"> </span><span class="n">y1</span><span class="p">);</span>
|
|||
|
|
<span class="w"> </span><span class="k">wait</span><span class="w"> </span><span class="p">(</span><span class="n">rdy2</span><span class="p">)</span><span class="w"> </span><span class="nb">$display</span><span class="p">(</span><span class="s">"y2=%d"</span><span class="p">,</span><span class="w"> </span><span class="n">y2</span><span class="p">);</span>
|
|||
|
|
<span class="w"> </span><span class="nb">$finish</span><span class="p">;</span>
|
|||
|
|
<span class="w"> </span><span class="k">end</span><span class="w"> </span><span class="c1">// initial begin</span>
|
|||
|
|
|
|||
|
|
<span class="k">endmodule</span><span class="w"> </span><span class="c1">// main</span>
|
|||
|
|
</pre></div>
|
|||
|
|
</div>
|
|||
|
|
<p>and the “sqrt_plusargs” program would be compiled and executed as follows:</p>
|
|||
|
|
<div class="highlight-none notranslate"><div class="highlight"><pre><span></span>% iverilog -osqrt_plusargs.vvp sqrt_plusargs.v sqrt.v
|
|||
|
|
% vvp sqrt_plusargs.vvp +x=81 +z=64
|
|||
|
|
y1= 9
|
|||
|
|
y2= 8
|
|||
|
|
</pre></div>
|
|||
|
|
</div>
|
|||
|
|
<p>In general, the “vvp” command that executes the compiled simulation takes a
|
|||
|
|
few predefined argument flags, then the file name of the simulation. All the
|
|||
|
|
arguments after the simulation file name are extended arguments to “vvp” and
|
|||
|
|
are passed to the executed design. Extended arguments that start with a “+”
|
|||
|
|
character are accessible through the “$test$plusargs” and “$value$plusargs”
|
|||
|
|
system functions. Extended arguments that do not start with a “+” character
|
|||
|
|
are only accessible to system tasks and functions written in C using the VPI.</p>
|
|||
|
|
<p>In the previous example, the program pulls the argument from the command line,
|
|||
|
|
assigns it to the variable “x”, and runs the sqrt device under test with that
|
|||
|
|
value. This program can take the integer square root of any single value. Of
|
|||
|
|
course, if you wish to test with a large number of input values, executing the
|
|||
|
|
program many times may become tedious.</p>
|
|||
|
|
<p>Another technique would be to put a set of input values into a data file, and
|
|||
|
|
write the test bench to read the file. We can then edit the file to add new
|
|||
|
|
input values, then rerun the simulation without compiling it again. The
|
|||
|
|
advantage of this technique is that we can accumulate a large set of test
|
|||
|
|
input values, and run the lot as a batch.</p>
|
|||
|
|
<p>This example</p>
|
|||
|
|
<div class="highlight-verilog notranslate"><div class="highlight"><pre><span></span><span class="k">module</span><span class="w"> </span><span class="n">main</span><span class="p">;</span>
|
|||
|
|
|
|||
|
|
<span class="w"> </span><span class="kt">reg</span><span class="w"> </span><span class="n">clk</span><span class="p">,</span><span class="w"> </span><span class="n">reset</span><span class="p">;</span>
|
|||
|
|
<span class="w"> </span><span class="kt">reg</span><span class="w"> </span><span class="p">[</span><span class="mh">31</span><span class="o">:</span><span class="mh">0</span><span class="p">]</span><span class="w"> </span><span class="n">data</span><span class="p">[</span><span class="mh">4</span><span class="o">:</span><span class="mh">0</span><span class="p">];</span>
|
|||
|
|
<span class="w"> </span><span class="kt">reg</span><span class="w"> </span><span class="p">[</span><span class="mh">31</span><span class="o">:</span><span class="mh">0</span><span class="p">]</span><span class="w"> </span><span class="n">x</span><span class="p">;</span>
|
|||
|
|
<span class="w"> </span><span class="kt">wire</span><span class="w"> </span><span class="p">[</span><span class="mh">15</span><span class="o">:</span><span class="mh">0</span><span class="p">]</span><span class="w"> </span><span class="n">y</span><span class="p">;</span>
|
|||
|
|
<span class="w"> </span><span class="kt">wire</span><span class="w"> </span><span class="n">rdy</span><span class="p">;</span>
|
|||
|
|
|
|||
|
|
<span class="w"> </span><span class="n">sqrt32</span><span class="w"> </span><span class="n">dut</span><span class="w"> </span><span class="p">(</span><span class="n">clk</span><span class="p">,</span><span class="w"> </span><span class="n">rdy</span><span class="p">,</span><span class="w"> </span><span class="n">reset</span><span class="p">,</span><span class="w"> </span><span class="n">x</span><span class="p">,</span><span class="w"> </span><span class="n">y</span><span class="p">);</span>
|
|||
|
|
|
|||
|
|
<span class="w"> </span><span class="k">always</span><span class="w"> </span><span class="p">#</span><span class="mh">10</span><span class="w"> </span><span class="n">clk</span><span class="w"> </span><span class="o">=</span><span class="w"> </span><span class="o">~</span><span class="n">clk</span><span class="p">;</span>
|
|||
|
|
|
|||
|
|
<span class="w"> </span><span class="k">integer</span><span class="w"> </span><span class="n">i</span><span class="p">;</span>
|
|||
|
|
<span class="w"> </span><span class="k">initial</span><span class="w"> </span><span class="k">begin</span>
|
|||
|
|
<span class="w"> </span><span class="cm">/* Load the data set from the hex file. */</span>
|
|||
|
|
<span class="w"> </span><span class="nb">$readmemh</span><span class="p">(</span><span class="s">"sqrt.hex"</span><span class="p">,</span><span class="w"> </span><span class="n">data</span><span class="p">);</span>
|
|||
|
|
<span class="w"> </span><span class="k">for</span><span class="w"> </span><span class="p">(</span><span class="n">i</span><span class="w"> </span><span class="o">=</span><span class="w"> </span><span class="mh">0</span><span class="w"> </span><span class="p">;</span><span class="w"> </span><span class="n">i</span><span class="w"> </span><span class="o"><=</span><span class="w"> </span><span class="mh">4</span><span class="w"> </span><span class="p">;</span><span class="w"> </span><span class="n">i</span><span class="w"> </span><span class="o">=</span><span class="w"> </span><span class="n">i</span><span class="w"> </span><span class="o">+</span><span class="w"> </span><span class="mh">1</span><span class="p">)</span><span class="w"> </span><span class="k">begin</span>
|
|||
|
|
<span class="w"> </span><span class="n">clk</span><span class="w"> </span><span class="o">=</span><span class="w"> </span><span class="mh">0</span><span class="p">;</span>
|
|||
|
|
<span class="w"> </span><span class="n">reset</span><span class="w"> </span><span class="o">=</span><span class="w"> </span><span class="mh">1</span><span class="p">;</span>
|
|||
|
|
|
|||
|
|
<span class="w"> </span><span class="n">x</span><span class="w"> </span><span class="o">=</span><span class="w"> </span><span class="n">data</span><span class="p">[</span><span class="n">i</span><span class="p">];</span>
|
|||
|
|
|
|||
|
|
<span class="w"> </span><span class="p">#</span><span class="mh">35</span><span class="w"> </span><span class="n">reset</span><span class="w"> </span><span class="o">=</span><span class="w"> </span><span class="mh">0</span><span class="p">;</span>
|
|||
|
|
|
|||
|
|
<span class="w"> </span><span class="k">wait</span><span class="w"> </span><span class="p">(</span><span class="n">rdy</span><span class="p">)</span><span class="w"> </span><span class="nb">$display</span><span class="p">(</span><span class="s">"y=%d"</span><span class="p">,</span><span class="w"> </span><span class="n">y</span><span class="p">);</span>
|
|||
|
|
<span class="w"> </span><span class="k">end</span>
|
|||
|
|
<span class="w"> </span><span class="nb">$finish</span><span class="p">;</span>
|
|||
|
|
<span class="w"> </span><span class="k">end</span><span class="w"> </span><span class="c1">// initial begin</span>
|
|||
|
|
|
|||
|
|
<span class="k">endmodule</span><span class="w"> </span><span class="c1">// main</span>
|
|||
|
|
</pre></div>
|
|||
|
|
</div>
|
|||
|
|
<p>demonstrates the use of “$readmemh” to read data samples from a file into a
|
|||
|
|
Verilog array. Start by putting into the file “sqrt.hex” the numbers:</p>
|
|||
|
|
<div class="highlight-none notranslate"><div class="highlight"><pre><span></span>51
|
|||
|
|
19
|
|||
|
|
1a
|
|||
|
|
18
|
|||
|
|
1
|
|||
|
|
</pre></div>
|
|||
|
|
</div>
|
|||
|
|
<p>Then run the simulation with the command sequence:</p>
|
|||
|
|
<div class="highlight-none notranslate"><div class="highlight"><pre><span></span>% iverilog -osqrt_readmem.vvp sqrt_readmem.vl sqrt.vl
|
|||
|
|
% vvp sqrt_readmem.vvp
|
|||
|
|
y= 9
|
|||
|
|
y= 5
|
|||
|
|
y= 5
|
|||
|
|
y= 4
|
|||
|
|
y= 1
|
|||
|
|
</pre></div>
|
|||
|
|
</div>
|
|||
|
|
<p>It is easy enough to change this program to work with larger data sets, or to
|
|||
|
|
change the “data.hex” file to contain different data. This technique is also
|
|||
|
|
common for simulating algorithms that take in larger data sets. One can extend
|
|||
|
|
this idea slightly by using a “$value$plusargs” statement to select the file
|
|||
|
|
to read.</p>
|
|||
|
|
</section>
|
|||
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|
|||
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