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iverilog/vhdlpp/vtype.cc

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Create the shell of a proper type system. Rather then just relying on comparing type names all throughout elaboration, create type description data structures and use them during elaboration to handle proper types.
2011-02-07 05:55:31 +01:00
/*
* Copyright (c) 2011 Stephen Williams (steve@icarus.com)
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
# include "vtype.h"
Elaborate array subtypes of ports. There are internal types that are unbounded arrays. Allow subtype syntax that creates bounded versions of these arrays, and elaborate them as vectors at port boundaries. This makes some interesting types work out. Also start replacing vhdlint and vhdlreal with int64_t and double, which are reasonable values for universal_integer and universal_real from the VHDL standard. I need these cleaned up because the ints in particular are used for the literal expressions in array index constraints.
2011-02-14 04:01:21 +01:00
# include <typeinfo>
Create the shell of a proper type system. Rather then just relying on comparing type names all throughout elaboration, create type description data structures and use them during elaboration to handle proper types.
2011-02-07 05:55:31 +01:00
using namespace std;
std::map<perm_string, const VType*> global_types;
const VTypePrimitive primitive_BOOLEAN (VTypePrimitive::BOOLEAN);
const VTypePrimitive primitive_BIT (VTypePrimitive::BIT);;
const VTypePrimitive primitive_INTEGER (VTypePrimitive::INTEGER);;
const VTypePrimitive primitive_STDLOGIC(VTypePrimitive::STDLOGIC);;
void preload_global_types(void)
{
global_types[perm_string::literal("boolean")] = &primitive_BOOLEAN;
global_types[perm_string::literal("bit")] = &primitive_BIT;
global_types[perm_string::literal("integer")] = &primitive_INTEGER;
global_types[perm_string::literal("std_logic")] = &primitive_STDLOGIC;
Do type mapping in the parser. In VHDL, types are declared before they are used, so it is possible to do type binding during parse. This makes the parser a little bit cleaner.
2011-02-14 01:37:10 +01:00
{ vector<VTypeArray::range_t> dims (1);
global_types[perm_string::literal("unsigned")] = new VTypeArray(&primitive_BIT, dims);
}
Create the shell of a proper type system. Rather then just relying on comparing type names all throughout elaboration, create type description data structures and use them during elaboration to handle proper types.
2011-02-07 05:55:31 +01:00
}
VType::~VType()
{
}
Elaborate array subtypes of ports. There are internal types that are unbounded arrays. Allow subtype syntax that creates bounded versions of these arrays, and elaborate them as vectors at port boundaries. This makes some interesting types work out. Also start replacing vhdlint and vhdlreal with int64_t and double, which are reasonable values for universal_integer and universal_real from the VHDL standard. I need these cleaned up because the ints in particular are used for the literal expressions in array index constraints.
2011-02-14 04:01:21 +01:00
void VType::show(ostream&out) const
{
out << typeid(*this).name();
}
Create the shell of a proper type system. Rather then just relying on comparing type names all throughout elaboration, create type description data structures and use them during elaboration to handle proper types.
2011-02-07 05:55:31 +01:00
VTypePrimitive::VTypePrimitive(VTypePrimitive::type_t tt)
: type_(tt)
{
}
VTypePrimitive::~VTypePrimitive()
{
}
Do type mapping in the parser. In VHDL, types are declared before they are used, so it is possible to do type binding during parse. This makes the parser a little bit cleaner.
2011-02-14 01:37:10 +01:00
Elaborate array subtypes of ports. There are internal types that are unbounded arrays. Allow subtype syntax that creates bounded versions of these arrays, and elaborate them as vectors at port boundaries. This makes some interesting types work out. Also start replacing vhdlint and vhdlreal with int64_t and double, which are reasonable values for universal_integer and universal_real from the VHDL standard. I need these cleaned up because the ints in particular are used for the literal expressions in array index constraints.
2011-02-14 04:01:21 +01:00
void VTypePrimitive::show(ostream&out) const
{
switch (type_) {
case BOOLEAN:
out << "BOOLEAN";
break;
case BIT:
out << "BIT";
break;
case INTEGER:
out << "INTEGER";
break;
case STDLOGIC:
out << "std_logic";
break;
}
}
Do type mapping in the parser. In VHDL, types are declared before they are used, so it is possible to do type binding during parse. This makes the parser a little bit cleaner.
2011-02-14 01:37:10 +01:00
VTypeArray::VTypeArray(const VType*element, const vector<VTypeArray::range_t>&r)
: etype_(element), ranges_(r)
{
}
VTypeArray::~VTypeArray()
{
}
Elaborate array subtypes of ports. There are internal types that are unbounded arrays. Allow subtype syntax that creates bounded versions of these arrays, and elaborate them as vectors at port boundaries. This makes some interesting types work out. Also start replacing vhdlint and vhdlreal with int64_t and double, which are reasonable values for universal_integer and universal_real from the VHDL standard. I need these cleaned up because the ints in particular are used for the literal expressions in array index constraints.
2011-02-14 04:01:21 +01:00
size_t VTypeArray::dimensions() const
{
return ranges_.size();
}
const VType* VTypeArray::element_type() const
{
return etype_;
}
void VTypeArray::show(ostream&out) const
{
out << "array ";
for (vector<range_t>::const_iterator cur = ranges_.begin()
; cur != ranges_.end() ; ++cur) {
out << "(" << cur->msb() << " downto " << cur->lsb() << ")";
}
out << " of ";
if (etype_)
etype_->show(out);
else
out << "<nil>";
}