60 lines
1.7 KiB
Markdown
60 lines
1.7 KiB
Markdown
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# Clocking blocks (Tier A #4)
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Status: **partial** — interface-local clocking enough for basic driver sync.
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## Supported in this slice
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```systemverilog
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interface bus_if(input logic clk);
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logic [7:0] data;
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logic req;
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clocking cb @(posedge clk);
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input #0 data; // #1step may be written; treated as #0
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output #0 req;
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endclocking
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endinterface
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module top;
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logic clk;
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bus_if bif(clk);
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logic [7:0] x;
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initial begin
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bif.data = 8'h3C;
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@(bif.cb); // wait on clocking event (posedge clk)
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bif.cb.req <= 1'b1; // NBA to underlying req
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x = bif.cb.data; // read current value of data
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end
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endmodule
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```
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### Pragmatic semantics (v1)
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| Construct | Behavior |
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|-----------|----------|
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| `@(cb)` / `@(bif.cb)` | Wait on the clocking event (`posedge clk`) |
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| `cb.req <= val` | Non-blocking assign to underlying `req` (visible after NBA / next clocking event) |
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| `cb.data` (read) | Current value of `data` (sampling skew = `#0`) |
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| `#0` / `#1step` skew | Accepted; `#1step` aliases to `#0` if present |
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Clocking signal names are **transparent** hierarchical hops: `bif.cb.req` resolves to `bif.req`.
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## Example
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[`examples/clocking/cb_basic.sv`](../examples/clocking/cb_basic.sv) — prints `PASSED`.
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```bash
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./install/bin/iverilog -g2012 -o /tmp/cb_basic.vvp examples/clocking/cb_basic.sv
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./install/bin/vvp /tmp/cb_basic.vvp
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```
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## Deferred (do not claim)
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- `default clocking`
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- `##` cycle delays
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- Modport clocking (`modport m (clocking cb);`)
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- Complex / non-zero input/output skews
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- `inout` clocking drive/sample timing
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- `vif.cb` through virtual interfaces (follow-on once VI member lookup covers clocking)
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See also [STATUS.md](STATUS.md) and [ROADMAP.md](ROADMAP.md).
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