iverilog/vvp/examples/set_reg.vvp

:vpi_module "system";

;
; This example demonstrates a simple blocking assignment to a
; reg vector within a module.
;


main    .scope module, "main" "main";

; This declares a "reg" data type named "test" in the current scope.
; The bit range is given for the purposes of VPI access. The range
; corresponds to the declaration "reg [7:0] test", so leads to an 8
; bit wide vector.
test	.var	"test", 7 0;

; The %set/v opcode writes a value to the target .var vector. The
; first operand is the label of the .var object. The second and
; third operands are the base and width of the bit set that is to
; be made into the vector to write.

T0	%set/v	test, 0, 8 ;
	%vpi_call 0 0 "$display", "test = %b", test;

	%set/v	test, 1, 8 ;
	%vpi_call 0 0 "$display", "test = %b", test;

	%set/v	test, 2, 8 ;
	%vpi_call 0 0 "$display", "test = %b", test;

	%set/v	test, 3, 8 ;
	%vpi_call 0 0 "$display", "test = %b", test;

	%end;
	.thread T0;
:file_names 2;
    "N/A";
    "<interactive>";