iverilog/vvp/examples/edge.vvp

:vpi_module "system";

; Copyright (c) 2001-2008  Stephen Williams (steve@icarus.com)
;
;    This source code is free software; you can redistribute it
;    and/or modify it in source code form under the terms of the GNU
;    General Public License as published by the Free Software
;    Foundation; either version 2 of the License, or (at your option)
;    any later version.
;
;    This program is distributed in the hope that it will be useful,
;    but WITHOUT ANY WARRANTY; without even the implied warranty of
;    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
;    GNU General Public License for more details.
;
;    You should have received a copy of the GNU General Public License
;    along with this program; if not, write to the Free Software
;    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA


; This example tests the operation of a simple posedge event. The module
; that would generate code like this would be:
;
;    module main;
;        reg a;
;
;        initial begin
;          a = 0;
;          #1 a = 1;
;        end
;
;        always @(posedge a) $display("Got a posedge.");
;
;    endmodule
;

main	.scope module, "main";

V_main.a	.var "a", 0 0;
V_main.b	.event posedge, V_main.a;

code
	%set/v V_main.a, 0, 1;
	%delay 1, 0;
	%set/v V_main.a, 1, 1;
	%end;
	.thread	code;

loop	%wait V_main.b;
	%vpi_call 0 0 "$display", "Got a posedge.";
	%jmp loop;
	.thread loop;
:file_names 2;
    "N/A";
    "<interactive>";