66 lines
1.8 KiB
C
66 lines
1.8 KiB
C
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#ifndef __PWire_H
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#define __PWire_H
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/*
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* Copyright (c) 1998 Stephen Williams (steve@icarus.com)
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*
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* This source code is free software; you can redistribute it
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* and/or modify it in source code form under the terms of the GNU
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* General Public License as published by the Free Software
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* Foundation; either version 2 of the License, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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#if !defined(WINNT)
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#ident "$Id: PWire.h,v 1.1 1998/11/03 23:28:55 steve Exp $"
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#endif
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# include "netlist.h"
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class ostream;
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class PExpr;
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class Design;
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/*
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* Wires include nets, registers and ports. A net or register becomes
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* a port by declaration, so ports are not seperate. The module
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* identifies a port by keeping it in its port list.
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*/
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class PWire {
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public:
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PWire(const string&n, NetNet::Type t =NetNet::IMPLICIT)
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: name(n), type(t), port_type(NetNet::NOT_A_PORT), msb(0), lsb(0)
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{ }
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string name;
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NetNet::Type type;
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NetNet::PortType port_type;
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PExpr*msb;
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PExpr*lsb;
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// Write myself to the specified stream.
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void dump(ostream&out) const;
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void elaborate(Design*, const string&path) const;
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private: // not implemented
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PWire(const PWire&);
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PWire& operator= (const PWire&);
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};
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/*
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* $Log: PWire.h,v $
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* Revision 1.1 1998/11/03 23:28:55 steve
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* Introduce verilog to CVS.
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*
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*/
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#endif
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