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iverilog/vhdlpp/vtype.h

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Create the shell of a proper type system. Rather then just relying on comparing type names all throughout elaboration, create type description data structures and use them during elaboration to handle proper types.
2011-02-07 05:55:31 +01:00
#ifndef __vtype_H
#define __vtype_H
/*
* Copyright (c) 2011 Stephen Williams (steve@icarus.com)
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
Elaborate array subtypes of ports. There are internal types that are unbounded arrays. Allow subtype syntax that creates bounded versions of these arrays, and elaborate them as vectors at port boundaries. This makes some interesting types work out. Also start replacing vhdlint and vhdlreal with int64_t and double, which are reasonable values for universal_integer and universal_real from the VHDL standard. I need these cleaned up because the ints in particular are used for the literal expressions in array index constraints.
2011-02-14 04:01:21 +01:00
# include <iostream>
Create the shell of a proper type system. Rather then just relying on comparing type names all throughout elaboration, create type description data structures and use them during elaboration to handle proper types.
2011-02-07 05:55:31 +01:00
# include <map>
Do type mapping in the parser. In VHDL, types are declared before they are used, so it is possible to do type binding during parse. This makes the parser a little bit cleaner.
2011-02-14 01:37:10 +01:00
# include <vector>
# include <climits>
Create the shell of a proper type system. Rather then just relying on comparing type names all throughout elaboration, create type description data structures and use them during elaboration to handle proper types.
2011-02-07 05:55:31 +01:00
# include "StringHeap.h"
Do type mapping in the parser. In VHDL, types are declared before they are used, so it is possible to do type binding during parse. This makes the parser a little bit cleaner.
2011-02-14 01:37:10 +01:00
/*
* A description of a VHDL type consists of a graph of VType
* objects. Derived types are specific kinds of types, and those that
* are compound may in turn reference other types.
*/
Create the shell of a proper type system. Rather then just relying on comparing type names all throughout elaboration, create type description data structures and use them during elaboration to handle proper types.
2011-02-07 05:55:31 +01:00
class VType {
public:
VType() { }
virtual ~VType() =0;
Elaborate array subtypes of ports. There are internal types that are unbounded arrays. Allow subtype syntax that creates bounded versions of these arrays, and elaborate them as vectors at port boundaries. This makes some interesting types work out. Also start replacing vhdlint and vhdlreal with int64_t and double, which are reasonable values for universal_integer and universal_real from the VHDL standard. I need these cleaned up because the ints in particular are used for the literal expressions in array index constraints.
2011-02-14 04:01:21 +01:00
virtual void show(std::ostream&) const;
Add more complete support for vhdl local signals. These signals are declared in the architecture and are local to the module. The Architecture already parsed and stored these signal declarations, but this patch adds the ability to actually emit these signals in the generated code. In the process of doing this, I had to regularize the elaboration and emit of VTypes, so that it can be used in multiple places, not just in entity headers (for ports). I also added support for bit selects of signals. This effected a couple places in the parser, and expressions in general.
2011-03-27 21:01:58 +02:00
public:
enum vtype_t { VNONE, VBOOL, VLOGIC };
struct decl_t {
public:
decl_t() : signed_flag(false), type(VNONE), msb(0), lsb(0) { }
int emit(std::ostream&out, perm_string name) const;
public:
bool signed_flag;
vtype_t type;
long msb, lsb;
};
virtual void elaborate(decl_t&decl) const =0;
Create the shell of a proper type system. Rather then just relying on comparing type names all throughout elaboration, create type description data structures and use them during elaboration to handle proper types.
2011-02-07 05:55:31 +01:00
};
Elaborate array subtypes of ports. There are internal types that are unbounded arrays. Allow subtype syntax that creates bounded versions of these arrays, and elaborate them as vectors at port boundaries. This makes some interesting types work out. Also start replacing vhdlint and vhdlreal with int64_t and double, which are reasonable values for universal_integer and universal_real from the VHDL standard. I need these cleaned up because the ints in particular are used for the literal expressions in array index constraints.
2011-02-14 04:01:21 +01:00
inline std::ostream&operator << (std::ostream&out, const VType&item)
{
item.show(out);
return out;
}
Create the shell of a proper type system. Rather then just relying on comparing type names all throughout elaboration, create type description data structures and use them during elaboration to handle proper types.
2011-02-07 05:55:31 +01:00
/*
* The global_types variable maps type names to a type
* definition. This is after the "use" statements bring in the types
* in included packages.
*/
extern std::map<perm_string, const VType*> global_types;
extern void preload_global_types(void);
Stub support for "use" directives. Implement the parser infrastructure for handling library use clauses, and use that to handle specific packages of the ieee library. Make the numeric types come from the numeric_* packages instead of being built in.
2011-02-19 22:08:26 +01:00
Stub support for library import. This provides a stub implementation for library import. Use this stub to make up a slightly more functional ieee library implementation.
2011-02-19 20:39:00 +01:00
extern void import_ieee(void);
Stub support for "use" directives. Implement the parser infrastructure for handling library use clauses, and use that to handle specific packages of the ieee library. Make the numeric types come from the numeric_* packages instead of being built in.
2011-02-19 22:08:26 +01:00
extern void import_ieee_use(perm_string package, perm_string name);
Create the shell of a proper type system. Rather then just relying on comparing type names all throughout elaboration, create type description data structures and use them during elaboration to handle proper types.
2011-02-07 05:55:31 +01:00
/*
* This class represents the primative types that are available to the
* type subsystem.
*/
class VTypePrimitive : public VType {
public:
enum type_t { BOOLEAN, BIT, INTEGER, STDLOGIC };
public:
VTypePrimitive(type_t);
~VTypePrimitive();
Elaborate array subtypes of ports. There are internal types that are unbounded arrays. Allow subtype syntax that creates bounded versions of these arrays, and elaborate them as vectors at port boundaries. This makes some interesting types work out. Also start replacing vhdlint and vhdlreal with int64_t and double, which are reasonable values for universal_integer and universal_real from the VHDL standard. I need these cleaned up because the ints in particular are used for the literal expressions in array index constraints.
2011-02-14 04:01:21 +01:00
void show(std::ostream&) const;
Add more complete support for vhdl local signals. These signals are declared in the architecture and are local to the module. The Architecture already parsed and stored these signal declarations, but this patch adds the ability to actually emit these signals in the generated code. In the process of doing this, I had to regularize the elaboration and emit of VTypes, so that it can be used in multiple places, not just in entity headers (for ports). I also added support for bit selects of signals. This effected a couple places in the parser, and expressions in general.
2011-03-27 21:01:58 +02:00
void elaborate(decl_t&decl) const;
Elaborate array subtypes of ports. There are internal types that are unbounded arrays. Allow subtype syntax that creates bounded versions of these arrays, and elaborate them as vectors at port boundaries. This makes some interesting types work out. Also start replacing vhdlint and vhdlreal with int64_t and double, which are reasonable values for universal_integer and universal_real from the VHDL standard. I need these cleaned up because the ints in particular are used for the literal expressions in array index constraints.
2011-02-14 04:01:21 +01:00
Create the shell of a proper type system. Rather then just relying on comparing type names all throughout elaboration, create type description data structures and use them during elaboration to handle proper types.
2011-02-07 05:55:31 +01:00
type_t type() const { return type_; }
private:
type_t type_;
};
extern const VTypePrimitive primitive_BOOLEAN;
extern const VTypePrimitive primitive_BIT;
extern const VTypePrimitive primitive_INTEGER;
extern const VTypePrimitive primitive_STDLOGIC;
Do type mapping in the parser. In VHDL, types are declared before they are used, so it is possible to do type binding during parse. This makes the parser a little bit cleaner.
2011-02-14 01:37:10 +01:00
/*
* An array is a compound N-dimensional array of element type. The
* construction of the array is from an element type and a vector of
* ranges. The array type can be left incomplete by leaving some
* ranges as "box" ranges, meaning present but not defined.
*/
Create the shell of a proper type system. Rather then just relying on comparing type names all throughout elaboration, create type description data structures and use them during elaboration to handle proper types.
2011-02-07 05:55:31 +01:00
class VTypeArray : public VType {
public:
Do type mapping in the parser. In VHDL, types are declared before they are used, so it is possible to do type binding during parse. This makes the parser a little bit cleaner.
2011-02-14 01:37:10 +01:00
class range_t {
public:
range_t() : msb_(INT_MAX), lsb_(INT_MIN) { }
range_t(int m, int l) : msb_(m), lsb_(l) { }
bool is_box() const { return msb_==INT_MAX && lsb_==INT_MIN; }
int msb() const { return msb_; }
int lsb() const { return lsb_; }
private:
int msb_;
int lsb_;
};
public:
Handle signed vs unsigned vector types. In principle, some of these should be handled by overloaded operator functions, but these are built in types with natural translations so do the obvious things.
2011-02-26 05:09:31 +01:00
VTypeArray(const VType*etype, const std::vector<range_t>&r, bool signed_vector =false);
Create the shell of a proper type system. Rather then just relying on comparing type names all throughout elaboration, create type description data structures and use them during elaboration to handle proper types.
2011-02-07 05:55:31 +01:00
~VTypeArray();
Elaborate array subtypes of ports. There are internal types that are unbounded arrays. Allow subtype syntax that creates bounded versions of these arrays, and elaborate them as vectors at port boundaries. This makes some interesting types work out. Also start replacing vhdlint and vhdlreal with int64_t and double, which are reasonable values for universal_integer and universal_real from the VHDL standard. I need these cleaned up because the ints in particular are used for the literal expressions in array index constraints.
2011-02-14 04:01:21 +01:00
void show(std::ostream&) const;
Add more complete support for vhdl local signals. These signals are declared in the architecture and are local to the module. The Architecture already parsed and stored these signal declarations, but this patch adds the ability to actually emit these signals in the generated code. In the process of doing this, I had to regularize the elaboration and emit of VTypes, so that it can be used in multiple places, not just in entity headers (for ports). I also added support for bit selects of signals. This effected a couple places in the parser, and expressions in general.
2011-03-27 21:01:58 +02:00
void elaborate(decl_t&decl) const;
Elaborate array subtypes of ports. There are internal types that are unbounded arrays. Allow subtype syntax that creates bounded versions of these arrays, and elaborate them as vectors at port boundaries. This makes some interesting types work out. Also start replacing vhdlint and vhdlreal with int64_t and double, which are reasonable values for universal_integer and universal_real from the VHDL standard. I need these cleaned up because the ints in particular are used for the literal expressions in array index constraints.
2011-02-14 04:01:21 +01:00
Create the shell of a proper type system. Rather then just relying on comparing type names all throughout elaboration, create type description data structures and use them during elaboration to handle proper types.
2011-02-07 05:55:31 +01:00
size_t dimensions() const;
Elaborate array subtypes of ports. There are internal types that are unbounded arrays. Allow subtype syntax that creates bounded versions of these arrays, and elaborate them as vectors at port boundaries. This makes some interesting types work out. Also start replacing vhdlint and vhdlreal with int64_t and double, which are reasonable values for universal_integer and universal_real from the VHDL standard. I need these cleaned up because the ints in particular are used for the literal expressions in array index constraints.
2011-02-14 04:01:21 +01:00
const range_t&dimension(size_t idx) const
{ return ranges_[idx]; }
Handle signed vs unsigned vector types. In principle, some of these should be handled by overloaded operator functions, but these are built in types with natural translations so do the obvious things.
2011-02-26 05:09:31 +01:00
bool signed_vector() const { return signed_flag_; }
Do type mapping in the parser. In VHDL, types are declared before they are used, so it is possible to do type binding during parse. This makes the parser a little bit cleaner.
2011-02-14 01:37:10 +01:00
const VType* element_type() const;
Create the shell of a proper type system. Rather then just relying on comparing type names all throughout elaboration, create type description data structures and use them during elaboration to handle proper types.
2011-02-07 05:55:31 +01:00
private:
Do type mapping in the parser. In VHDL, types are declared before they are used, so it is possible to do type binding during parse. This makes the parser a little bit cleaner.
2011-02-14 01:37:10 +01:00
const VType*etype_;
std::vector<range_t> ranges_;
Handle signed vs unsigned vector types. In principle, some of these should be handled by overloaded operator functions, but these are built in types with natural translations so do the obvious things.
2011-02-26 05:09:31 +01:00
bool signed_flag_;
Create the shell of a proper type system. Rather then just relying on comparing type names all throughout elaboration, create type description data structures and use them during elaboration to handle proper types.
2011-02-07 05:55:31 +01:00
};
#endif