71 lines
2.1 KiB
Plaintext
71 lines
2.1 KiB
Plaintext
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FPGA LOADABLE CODE GENERATOR FOR Icarus Verilog
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Copyright 2001 Stephen Williams
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$Id: fpga.txt,v 1.1 2001/09/02 23:58:49 steve Exp $
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INVOKING THE FPGA TARGET
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This code generator is invoked with the -tfpga flag to iverilog. The
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code generator understands the part= and the arch= parameters, which
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can be set with the -p flag of iverilog:
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iverilog -parch=virtex -fpart=v50-pq240-6 -tfpga foo.vl
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* arch=generic-xnf
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If this is selected, then the output is formatted as an XNF file,
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suitable for most any type of device. The devices that it emits
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are generic devices from the unified library. Some devices are macros,
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you will may need to further resolve the generated XNF to get working
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code for your part.
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* arch=virtex
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If this is selected, then the output is formatted as an EDIF 200 file,
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suitable for Virtex class devices. This is supposed to know that you
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are targeting a Virtex part, so can generate primitives instead of
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using external macros.
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XNF ROOT PORTS
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When the output format is XNF, the code generator will generate "SIG"
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records for the signals that are ports of the root module. The name is
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declared as an external pin that this macro makes available.
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The name given to the macro pin is generated from the base name of the
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signal. If the signal is one bit wide, then the pin name is exactly
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the module port name. If the port is a vector, then the pin number is
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given as a vector. For example, the module:
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module main(out, in);
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output out;
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input [2:0] in;
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[...]
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endmodule
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leads to these SIG, records:
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SIG, main/out, PIN=out
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SIG, main/in<2>, PIN=in2
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SIG, main/in<1>, PIN=in1
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SIG, main/in<0>, PIN=in0
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EDIF ROOT PORTS
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The EDIF format is more explicit about the interface into an EDIF
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file. The code generator uses that control to generate an explicit
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interface definition into the design. (This is *not* the same as the
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PADS of a part.) The generated EDIF interface section contains port
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definitions, including the proper direction marks.
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---
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$Log: fpga.txt,v $
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Revision 1.1 2001/09/02 23:58:49 steve
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Add documentation for the code generator.
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