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iverilog/vhdlpp/vtype_emit.cc

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Add more complete support for vhdl local signals. These signals are declared in the architecture and are local to the module. The Architecture already parsed and stored these signal declarations, but this patch adds the ability to actually emit these signals in the generated code. In the process of doing this, I had to regularize the elaboration and emit of VTypes, so that it can be used in multiple places, not just in entity headers (for ports). I also added support for bit selects of signals. This effected a couple places in the parser, and expressions in general.
2011-03-27 21:01:58 +02:00
/*
* Copyright (c) 2011 Stephen Williams (steve@icarus.com)
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
# include "vtype.h"
# include <iostream>
# include <typeinfo>
# include <cassert>
using namespace std;
int VType::decl_t::emit(ostream&out, perm_string name) const
{
Arrange for ports used as l-values to be declared as "reg". Entity output ports may be used as l-values in a process within the bound architecture. Detect that case during elaboration and adjust the signal declaration so that it works in the Verilog pass.
2011-05-16 01:17:51 +02:00
const char*wire = reg_flag? "reg" : "wire";
Add more complete support for vhdl local signals. These signals are declared in the architecture and are local to the module. The Architecture already parsed and stored these signal declarations, but this patch adds the ability to actually emit these signals in the generated code. In the process of doing this, I had to regularize the elaboration and emit of VTypes, so that it can be used in multiple places, not just in entity headers (for ports). I also added support for bit selects of signals. This effected a couple places in the parser, and expressions in general.
2011-03-27 21:01:58 +02:00
switch (type) {
case VType::VNONE:
out << "// N type for " << name << endl;
break;
case VType::VLOGIC:
Arrange for ports used as l-values to be declared as "reg". Entity output ports may be used as l-values in a process within the bound architecture. Detect that case during elaboration and adjust the signal declaration so that it works in the Verilog pass.
2011-05-16 01:17:51 +02:00
out << wire<< " logic ";
Add more complete support for vhdl local signals. These signals are declared in the architecture and are local to the module. The Architecture already parsed and stored these signal declarations, but this patch adds the ability to actually emit these signals in the generated code. In the process of doing this, I had to regularize the elaboration and emit of VTypes, so that it can be used in multiple places, not just in entity headers (for ports). I also added support for bit selects of signals. This effected a couple places in the parser, and expressions in general.
2011-03-27 21:01:58 +02:00
if (signed_flag)
out << "signed ";
if (msb != lsb)
out << "[" << msb << ":" << lsb << "] ";
Emit VHDL symbols as escaped identifiers
2011-08-20 21:11:49 +02:00
out << "\\" << name << " ";
Add more complete support for vhdl local signals. These signals are declared in the architecture and are local to the module. The Architecture already parsed and stored these signal declarations, but this patch adds the ability to actually emit these signals in the generated code. In the process of doing this, I had to regularize the elaboration and emit of VTypes, so that it can be used in multiple places, not just in entity headers (for ports). I also added support for bit selects of signals. This effected a couple places in the parser, and expressions in general.
2011-03-27 21:01:58 +02:00
break;
case VType::VBOOL:
Arrange for ports used as l-values to be declared as "reg". Entity output ports may be used as l-values in a process within the bound architecture. Detect that case during elaboration and adjust the signal declaration so that it works in the Verilog pass.
2011-05-16 01:17:51 +02:00
out << wire << " bool ";
Add more complete support for vhdl local signals. These signals are declared in the architecture and are local to the module. The Architecture already parsed and stored these signal declarations, but this patch adds the ability to actually emit these signals in the generated code. In the process of doing this, I had to regularize the elaboration and emit of VTypes, so that it can be used in multiple places, not just in entity headers (for ports). I also added support for bit selects of signals. This effected a couple places in the parser, and expressions in general.
2011-03-27 21:01:58 +02:00
if (signed_flag)
out << "signed ";
if (msb != lsb)
out << "[" << msb << ":" << lsb << "] ";
Emit VHDL symbols as escaped identifiers
2011-08-20 21:11:49 +02:00
out << "\\" << name << " ";
Add more complete support for vhdl local signals. These signals are declared in the architecture and are local to the module. The Architecture already parsed and stored these signal declarations, but this patch adds the ability to actually emit these signals in the generated code. In the process of doing this, I had to regularize the elaboration and emit of VTypes, so that it can be used in multiple places, not just in entity headers (for ports). I also added support for bit selects of signals. This effected a couple places in the parser, and expressions in general.
2011-03-27 21:01:58 +02:00
break;
}
return 0;
}