9 lines
178 B
Coq
9 lines
178 B
Coq
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module test();
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wire clk;
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reg [8:0] lowp2_tmp;
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reg [8:0] lowp2_out;
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always @(posedge clk) begin
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lowp2_out <= ( {lowp2_tmp[8], lowp2_tmp} ) >> 1;
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end
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endmodule
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