25 lines
579 B
VHDL
25 lines
579 B
VHDL
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library ieee;
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use ieee.std_logic_1164.all;
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package work7 is
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-- D-type flip flop
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component fdc is
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port (clk: in std_logic;
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reset: in std_logic;
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d: in std_logic;
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q: out std_logic);
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end component;
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component TimeBase is
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port(
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CLOCK : in std_logic; -- input clock of 20MHz
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TICK : out std_logic; -- out 1 sec timebase signal
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RESET : in std_logic; -- master reset signal (active high)
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ENABLE : in std_logic;
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COUNT_VALUE: out std_logic_vector (24 downto 0)
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);
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end component;
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end package work7;
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