43 lines
1.5 KiB
VHDL
43 lines
1.5 KiB
VHDL
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-- Copyright (c) 2014 CERN
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-- Maciej Suminski <maciej.suminski@cern.ch>
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--
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-- This source code is free software; you can redistribute it
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-- and/or modify it in source code form under the terms of the GNU
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-- General Public License as published by the Free Software
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-- Foundation; either version 2 of the License, or (at your option)
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-- any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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-- Basic test for the unbounded arrays in VHDL.
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library ieee;
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use ieee.std_logic_1164.all;
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entity vhdl_unbounded_array is
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end vhdl_unbounded_array;
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architecture test of vhdl_unbounded_array is
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-- This can be translated as an unpacked array in SystemVerilog
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type unb_logic is array (integer range <>) of std_logic;
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-- These have to be packed arrays
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type unb_integer is array (natural range <>) of integer;
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type unb_real is array (integer range <>) of real;
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signal sig_logic : unb_logic(7 downto 0);
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signal sig_integer : unb_integer(3 downto 0);
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signal sig_real : unb_real(0 to 3);
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begin
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sig_logic <= "01010101";
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sig_integer(2) <= 1;
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sig_real(1) <= 2.5;
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end architecture test;
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