85 lines
2.9 KiB
VHDL
85 lines
2.9 KiB
VHDL
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-- Copyright (c) 2015-2016 CERN
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-- Maciej Suminski <maciej.suminski@cern.ch>
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--
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-- This source code is free software; you can redistribute it
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-- and/or modify it in source code form under the terms of the GNU
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-- General Public License as published by the Free Software
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-- Foundation; either version 2 of the License, or (at your option)
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-- any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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-- Test reading files using std.textio library.
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use std.textio.all;
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entity vhdl_textio_read is
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port(
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clk, active : in std_logic;
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line_counter : out integer;
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ok : out std_logic
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);
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end vhdl_textio_read;
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architecture test of vhdl_textio_read is
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begin
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read_data: process(clk, active)
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file data_file : text;
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variable data_line : line;
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variable data_string : string(6 downto 1);
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variable data_int, data_hex : integer;
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variable data_bool : boolean;
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variable data_real : real;
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variable data_time : time;
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variable data_logic : std_logic_vector(5 downto 0);
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begin
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if rising_edge(active) then
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file_open(data_file, "vhdl_textio.tmp", read_mode);
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line_counter := 0;
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elsif falling_edge(active) then
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file_close(data_file);
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end if;
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if rising_edge(clk) and active = '1' then
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readline(data_file, data_line);
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line_counter := line_counter + 1;
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case line_counter is
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-- Test reading different variable types
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when 1 => read(data_line, data_int);
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when 2 => read(data_line, data_bool);
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when 3 => read(data_line, data_time);
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when 4 => hread(data_line, data_hex);
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when 5 => read(data_line, data_real);
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when 6 => read(data_line, data_string);
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when 7 =>
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read(data_line, data_logic);
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-- Verify the read data
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if data_int = 123
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and data_bool = true
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and data_time = 100 s
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and data_hex = x"f3"
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and data_real = 12.21
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and data_string = "string"
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and data_logic = "1100XZ" then
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ok <= '1';
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end if;
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end case;
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end if;
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end process;
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end test;
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