68 lines
1.5 KiB
Coq
68 lines
1.5 KiB
Coq
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//
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// Author: Pawel Szostek (pawel.szostek@cern.ch)
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// Date: 01.08.2011
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`timescale 1ns/1ps
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module dummy_v( input [7:0] in, output reg [7:0] out);
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assign out = {in[7], 7'b1111111}; //there is no equivalent to vhdl's `others'
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endmodule
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module stimulus (output reg [7:0] a);
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parameter S = 20000;
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int unsigned j,i;
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initial begin
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for(i=0; i<S; i=i+1) begin
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#10;
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a[7] <= inject();
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a[6] <= inject();
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a[5] <= inject();
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a[4] <= inject();
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a[3] <= inject();
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a[2] <= inject();
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a[1] <= inject();
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a[0] <= inject();
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end
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end
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function inject();
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reg ret;
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reg unsigned [3:0] temp;
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temp[3:0] = $random % 16;
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begin
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if(temp >= 10)
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ret = 1'b1;
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else if(temp >= 4)
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ret = 1'b0;
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else if(temp >= 2)
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ret = 1'bx;
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else
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ret = 1'b0;
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inject = ret;
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end
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endfunction
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endmodule
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module main;
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wire [7:0] i,o;
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wire [7:0] veri;
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dummy dummy_vhdl(i,o);
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dummy_v dummy_verilog(i, veri);
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stimulus stim(i);
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always @(i) begin
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#1;
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if(o != veri) begin
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$display("ERROR!");
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$display("VERILOG: ", veri);
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$display("VHDL: ", o);
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$stop;
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end
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end
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initial begin
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#12000;
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#10;
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$display("PASSED");
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//stop;
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end
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endmodule
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