19 lines
363 B
VHDL
19 lines
363 B
VHDL
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--
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-- Author: Pawel Szostek (pawel.szostek@cern.ch)
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-- Date: 27.07.2011
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity dummy is
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port (o1: out std_logic_vector(7 downto 0); -- intentionally messed indices
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i1: in std_logic_vector(0 to 7) --
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);
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end;
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architecture behaviour of dummy is
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begin
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o1 <= i1;
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end;
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