52 lines
1.8 KiB
VHDL
52 lines
1.8 KiB
VHDL
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-- Copyright (c) 2014 CERN
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-- Maciej Suminski <maciej.suminski@cern.ch>
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--
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-- This source code is free software; you can redistribute it
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-- and/or modify it in source code form under the terms of the GNU
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-- General Public License as published by the Free Software
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-- Foundation; either version 2 of the License, or (at your option)
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-- any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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-- Tests for various subprogram features.
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library ieee;
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use ieee.std_logic_1164.all;
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-- tests subprograms imported from an external library
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use work.subprogram_pkg.all;
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entity subprogram is
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end;
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architecture behaviour of subprogram is
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function negate(input_word : std_logic_vector(7 downto 0))
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-- tests using undefined size std_logic_vector as a return type
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return std_logic_vector is
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-- tests variable declaration in subprograoms
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variable output_word : std_logic_vector(7 downto 0);
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begin
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for i in 7 downto 0 loop
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-- tests distuingishing between vector and function call basing on the
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-- function parameter
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output_word(i) := not input_word(i);
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end loop;
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return output_word;
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end function;
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signal negated : std_logic_vector(7 downto 0);
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signal reversed : std_logic_vector(7 downto 0);
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begin
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-- parameter type is determined by checking the parameter type in function declaration
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negated <= negate("11000111");
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reversed <= reverse("10000111");
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end;
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