42 lines
966 B
VHDL
42 lines
966 B
VHDL
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library ieee;
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use ieee.std_logic_1164.all;
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entity foo_entity is
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port (
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i_low0: in std_logic_vector (3 downto 0);
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i_high0: in std_logic_vector (3 downto 0);
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i_low1: in std_logic_vector (3 downto 0);
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i_high1: in std_logic_vector (3 downto 0);
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o_low0: out std_logic_vector (3 downto 0);
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o_high0: out std_logic_vector (3 downto 0);
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o_low1: out std_logic_vector (3 downto 0);
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o_high1: out std_logic_vector (3 downto 0)
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);
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end foo_entity;
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architecture beh of foo_entity is
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type word is record
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high: std_logic_vector (3 downto 0);
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low: std_logic_vector (3 downto 0);
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end record;
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type dword is array (1 downto 0) of word;
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signal my_dword: dword;
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begin
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-- inputs
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my_dword(0).low <= i_low0;
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my_dword(0).high <= i_high0;
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my_dword(1).low <= i_low1;
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my_dword(1).high <= i_high1;
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-- outputs
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o_low0 <= my_dword(0).low;
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o_high0 <= my_dword(0).high;
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o_low1 <= my_dword(1).low;
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o_high1 <= my_dword(1).high;
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end beh;
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