33 lines
988 B
VHDL
33 lines
988 B
VHDL
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-- This VHDL was converted from Verilog using the
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-- Icarus Verilog VHDL Code Generator 0.10.0 (devel) (s20090923-656-gce5c263)
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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-- Generated from Verilog module test (foo.v:3)
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entity test is
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port (
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i : in unsigned(3 downto 0);
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o : out std_logic
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);
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end entity;
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-- Generated from Verilog module test (foo.v:3)
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architecture from_verilog of test is
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signal tmp_s1 : std_logic; -- Temporary created at foo.v:6
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signal tmp_s11 : std_logic; -- Temporary created at foo.v:6
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signal tmp_s3 : std_logic; -- Temporary created at foo.v:6
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signal tmp_s4 : std_logic; -- Temporary created at foo.v:6
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signal tmp_s7 : std_logic; -- Temporary created at foo.v:6
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signal tmp_s8 : std_logic; -- Temporary created at foo.v:6
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begin
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tmp_s4 <= tmp_s1 and tmp_s3;
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tmp_s8 <= tmp_s4 and tmp_s7;
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o <= tmp_s8 and tmp_s11;
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tmp_s1 <= i(3);
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tmp_s3 <= i(2);
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tmp_s7 <= i(1);
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tmp_s11 <= i(0);
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end architecture;
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