117 lines
2.5 KiB
VHDL
117 lines
2.5 KiB
VHDL
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library ieee;
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use ieee.std_logic_1164.all;
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package work6 is
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-- full 1-bit adder
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component fa1 is
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port (a_i, b_i, c_i: in std_logic;
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s_o, c_o: out std_logic);
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end component fa1;
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-- D-type flip flop
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component fdc is
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port (clk: in std_logic;
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reset: in std_logic;
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d: in std_logic;
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q: out std_logic);
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end component;
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-- doing nothing at the moment
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constant N: integer range 0 to 16 := 4;
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end package work6;
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-- a 1-bit Moore-type adder to be used in
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-- a serial adder FSM-driven architecture
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-- ________ _____
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-- a_i -->| |------>|D Q|---> s_o
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-- b_i -->| FA1 | | |
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-- | |--- | |
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-- ---> |_______| | |_____|
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--rst __|_______________________|
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-- | | |
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-- | | |
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-- | | | ______
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-- | | ---->|D Q|---
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-- | | | | |
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-- | | | | |
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-- | | |_____| |
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-- | |____________| |
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-- |________________________________|
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--
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library ieee;
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use ieee.std_logic_1164.all;
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use work.work6.all;
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entity sa1 is
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port (clk, reset: in std_logic;
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a_i, b_i: in std_logic;
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s_o: out std_logic
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);
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end entity sa1;
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architecture sa1_rtl of sa1 is
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signal sum, carry, carry_reg: std_logic;
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begin
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a1: fa1 port map (c_i => carry_reg,
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a_i => a_i,
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b_i => b_i,
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s_o => sum,
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c_o => carry
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);
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f1: fdc port map (clk => clk, reset => reset, d => sum, q => s_o);
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f2: fdc port map (clk => clk, reset => reset, d => carry, q => carry_reg);
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end architecture sa1_rtl;
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-- a one bit full adder written according to
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-- textbook's boolean equations
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library ieee;
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use ieee.std_logic_1164.all;
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entity fa1 is
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port (a_i, b_i, c_i: in std_logic;
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s_o, c_o: out std_logic
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);
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end entity fa1;
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architecture fa1_rtl of fa1 is
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begin
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s_o <= a_i xor b_i xor c_i;
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c_o <= (a_i and b_i) or (c_i and (a_i xor b_i));
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end architecture fa1_rtl;-- a D-type flip-flop with synchronous reset
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library ieee;
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use ieee.std_logic_1164.all;
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entity fdc is
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port (clk: in std_logic;
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reset: in std_logic;
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d: in std_logic;
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q: out std_logic
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);
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end fdc;
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architecture fdc_rtl of fdc is
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begin
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i_finish: process (clk)
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begin
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if (clk'event and clk = '1') then
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if (reset = '1') then
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q <= '0';
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else
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q <= d;
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end if;
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end if;
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end process;
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end fdc_rtl;
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