110 lines
2.2 KiB
Coq
110 lines
2.2 KiB
Coq
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// This module generates M pairs of N-1 bits unsigned numbers A, B
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// and also serialises them starting from LSB bits between
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// activation of active-high reset signal
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module stimulus #(parameter N = 4, M = 10) (input clk,
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output reg reset,
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output reg sa, sb,
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output reg unsigned [N-1:0] A, B );
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parameter D = 5;
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int unsigned i;
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reg unsigned [N-1:0] r1, r2;
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initial begin
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repeat(M) begin
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r1 = {$random} % N;
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r2 = {$random} % N;
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do_items(r1, r2);
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end
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end
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task do_items (input unsigned [N-1:0] v1, v2);
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begin
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A = 0; B = 0; reset = 0;
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do_reset();
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A = v1; B = v2;
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for (i=0; i<N; i=i+1) begin
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#2 sa = A[i];
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sb = B[i];
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@(posedge clk);
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end
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#2 sa = 1'b0;
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sb = 1'b0;
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@(posedge clk);
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end
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endtask
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task do_reset;
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begin
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@(posedge clk);
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@(negedge clk) reset = 1'b1;
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repeat(D) @(negedge clk);
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reset = 1'b0;
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end
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endtask
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endmodule
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// This module takes M pairs of N-1 bits unsigned numbers A, B and a serial stream ss
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// then it checks that following a negedge of a reset, after N positive clock cycles
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// the reconstuction of N ss bits is equal to A+B.
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module check #(parameter N = 4, M = 10)(input clk, reset, input unsigned [N-1:0] A, B, input ss);
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reg unsigned [N:0] psum;
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reg unsigned [N:0] ssum;
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int unsigned i;
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initial begin
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repeat(M)
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check_item();
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end
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task check_item;
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begin
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@(posedge reset);
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@(negedge reset);
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#2;
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psum = A + B;
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for (i=0; i<=N; i=i+1) begin
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@(posedge clk);
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#1;
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ssum[i] = ss;
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end
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if (psum != ssum) begin
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$display("ERROR");
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$finish;
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end
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end
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endtask
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endmodule
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module test;
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parameter N = 8, M = 25;
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parameter T = 10;
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parameter S = (N+1+6)*M*T + 100; // 6 is duration of a reset
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reg reset, clk;
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wire sa, sb, ss;
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wire [N-1:0] A, B;
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initial begin
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clk = 0;
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forever #(T/2) clk = ~clk;
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end
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stimulus #(N, M) stim (.clk(clk), .reset(reset), .sa(sa), .sb(sb), .A(A), .B(B));
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sa1 duv (.clk(clk), .reset(reset), .a_i(sa), .b_i(sb), .s_o(ss) );
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check #(N, M) check (.clk(clk), .reset(reset), .A(A), .B(B), .ss(ss));
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initial begin
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#S;
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$display("PASSED");
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$finish;
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end
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endmodule
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