51 lines
1.6 KiB
VHDL
51 lines
1.6 KiB
VHDL
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-- Copyright (c) 2015 CERN
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-- Maciej Suminski <maciej.suminski@cern.ch>
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--
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-- This source code is free software; you can redistribute it
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-- and/or modify it in source code form under the terms of the GNU
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-- General Public License as published by the Free Software
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-- Foundation; either version 2 of the License, or (at your option)
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-- any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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-- Example to test prefix for VTypeArray (and using function as index).
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library ieee;
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use ieee.std_logic_1164.all;
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entity prefix_array is
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port(sel_word : in std_logic_vector(1 downto 0);
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out_word : out integer);
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end entity prefix_array;
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architecture test of prefix_array is
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type t_timeouts is
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record
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a : integer;
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b : integer;
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end record;
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type t_timeouts_table is array (natural range <>) of t_timeouts;
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constant c_TIMEOUTS_TABLE : t_timeouts_table(3 downto 0) :=
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(0 => (a => 1, b => 2),
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1 => (a => 3, b => 4),
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2 => (a => 5, b => 6),
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3 => (a => 7, b => 8));
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begin
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process(sel_word)
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begin
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out_word <= to_unsigned((c_TIMEOUTS_TABLE(to_integer(unsigned(sel_word))).a), 32);
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end process;
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end architecture test;
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