17 lines
270 B
VHDL
17 lines
270 B
VHDL
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library IEEE;
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use IEEE.numeric_bit.all;
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entity or_gate is
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port (
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a_i : in bit; -- inputs
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b_i : in bit;
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c_o : out bit -- output
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);
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end entity or_gate;
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architecture rtl of or_gate is
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begin
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c_o <= a_i or b_i;
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end architecture rtl;
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