40 lines
1.4 KiB
VHDL
40 lines
1.4 KiB
VHDL
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-- Copyright (c) 2014 CERN
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-- Maciej Suminski <maciej.suminski@cern.ch>
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--
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-- This source code is free software; you can redistribute it
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-- and/or modify it in source code form under the terms of the GNU
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-- General Public License as published by the Free Software
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-- Foundation; either version 2 of the License, or (at your option)
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-- any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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-- Tests signal initializers.
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library ieee;
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use ieee.std_logic_1164.all;
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entity vhdl_init is
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end;
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architecture test of vhdl_init is
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-- Convert string to bitstring in initalizer
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signal a : std_logic_vector(7 downto 0) := "11101001";
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-- Initialize with aggregate expression
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signal b : std_logic_vector(3 downto 0) := (0 => '0', 3 => '1', 1 => '1', 2 => '0');
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-- Initialize with aggregate expression, inverted range
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signal c : std_logic_vector(0 to 3) := (3 => '1', others => '0');
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begin
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-- Architecture statement part cannot be empty
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-- Assign the previous value, otherwise you will get unknown value
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a <= "11101001";
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end test;
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