80 lines
2.1 KiB
VHDL
80 lines
2.1 KiB
VHDL
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-- Copyright (c) 2015 CERN
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-- Maciej Suminski <maciej.suminski@cern.ch>
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--
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-- This source code is free software; you can redistribute it
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-- and/or modify it in source code form under the terms of the GNU
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-- General Public License as published by the Free Software
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-- Foundation; either version 2 of the License, or (at your option)
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-- any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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-- Test for generics evaluation.
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library ieee;
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use ieee.std_logic_1164.all;
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entity eval_generic is
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generic(
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msb : integer range 1 to 7 := 7;
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bit_select : integer range 0 to 7 := 3
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);
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port(
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in_word : in std_logic_vector(msb downto 0);
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out_bit : out std_logic
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);
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end entity eval_generic;
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architecture test of eval_generic is
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begin
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out_bit <= in_word(bit_select);
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end architecture test;
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library ieee;
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use ieee.std_logic_1164.all;
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entity test_eval_generic is
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port(
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in_word : in std_logic_vector(7 downto 0);
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out_bit_def, out_bit_ovr : out std_logic
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);
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end entity test_eval_generic;
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architecture test of test_eval_generic is
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constant const_int : integer := 7;
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component eval_generic is
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generic(
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msb : integer range 1 to 7;
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bit_select : integer range 0 to 7
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);
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port(
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in_word : in std_logic_vector(msb downto 0);
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out_bit : out std_logic
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);
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end component eval_generic;
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begin
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override_test_unit: eval_generic
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generic map(bit_select => 2,
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msb => const_int)
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port map(
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in_word => (others => '1'),
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out_bit => out_bit_ovr
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);
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default_test_unit: eval_generic
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port map(
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in_word => in_word,
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out_bit => out_bit_def
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);
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end architecture test;
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