103 lines
2.5 KiB
VHDL
103 lines
2.5 KiB
VHDL
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-- In this test, we declare a component in the "mypackage" package
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-- and show that it can be referenced within the package namespace.
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-- it also shows the usage of subtypes, constants and signals
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-- expressed in terms of defined subtypes
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library ieee;
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use ieee.numeric_bit.all;
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package mypackage is
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-- trivial sub type
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subtype Myrange_t is integer range 0 to 4;
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-- some constants
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constant ZERO: Myrange_t := 0;
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constant ONE: Myrange_t := 1;
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constant TWO: Myrange_t := 2;
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constant THREE: Myrange_t := 3;
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constant FOUR: Myrange_t := 4;
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-- another subtype
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subtype AdderWidth_t is bit_vector (THREE downto ZERO);
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subtype CarryWidth_t is bit_vector (THREE+1 downto ZERO);
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-- full 1-bit adder
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component fa1 is
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port (a_i, b_i, c_i: in bit;
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s_o, c_o: out bit);
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end component fa1;
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end package mypackage;
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-- Declare and implement a 4-bit full-adder that uses the
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-- 1-bit full-adder described above.
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use work.mypackage.all;
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entity fa4 is
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port (va_i, vb_i: in AdderWidth_t;
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c_i: in bit;
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vs_o: out AdderWidth_t;
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c_o: out bit
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);
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end entity fa4;
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architecture fa4_rtl of fa4 is
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-- auxiliary signal for carry
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signal c_int: CarryWidth_t;
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begin
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-- carry in
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c_int(ZERO) <= c_i;
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-- slice 0
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s0: fa1 port map (c_i => c_int(ZERO),
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a_i => va_i(ZERO),
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b_i => vb_i(ZERO),
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s_o => vs_o(ZERO),
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c_o => c_int(ONE)
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);
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-- slice 1
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s1: fa1 port map (c_i => c_int(ONE),
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a_i => va_i(ONE),
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b_i => vb_i(ONE),
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s_o => vs_o(ONE),
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c_o => c_int(TWO)
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);
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-- slice 2
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s2: fa1 port map (c_i => c_int(TWO),
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a_i => va_i(TWO),
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b_i => vb_i(TWO),
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s_o => vs_o(TWO),
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c_o => c_int(THREE)
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);
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-- slice 3
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s3: fa1 port map (c_i => c_int(THREE),
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a_i => va_i(THREE),
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b_i => vb_i(THREE),
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s_o => vs_o(THREE),
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c_o => c_int(FOUR)
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);
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-- carry out
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c_o <= c_int(FOUR);
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end architecture fa4_rtl;
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-- Declare a 1-bit full-adder.
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entity fa1 is
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port (a_i, b_i, c_i: in bit;
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s_o, c_o: out bit
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);
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end entity fa1;
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architecture fa1_rtl of fa1 is
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begin
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s_o <= a_i xor b_i xor c_i;
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c_o <= (a_i and b_i) or (c_i and (a_i xor b_i));
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end architecture fa1_rtl;
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