33 lines
1.2 KiB
VHDL
33 lines
1.2 KiB
VHDL
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-- Copyright (c) 2014 CERN
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-- Maciej Suminski <maciej.suminski@cern.ch>
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--
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-- This source code is free software; you can redistribute it
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-- and/or modify it in source code form under the terms of the GNU
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-- General Public License as published by the Free Software
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-- Foundation; either version 2 of the License, or (at your option)
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-- any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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-- Tests if constants in packages can be initialized with expressions
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-- that normally require elaboration to be properly emitted.
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library IEEE;
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use IEEE.STD_LOGIC_1164.all;
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package const_package_pkg is
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constant c_bitstring : std_logic_vector(3 downto 0) := "1001";
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constant c_aggregate : std_logic_vector(7 downto 0) := (7 => '1', 3 => '1', others => '0');
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end const_package_pkg;
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package body const_package_pkg is
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end const_package_pkg;
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