17 lines
295 B
VHDL
17 lines
295 B
VHDL
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library IEEE;
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use IEEE.std_logic_1164.all;
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entity and_gate is
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port (
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a_i : in std_logic; -- inputs
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b_i : in std_logic;
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c_o : out std_logic -- output
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);
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end entity and_gate;
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architecture rtl of and_gate is
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begin
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c_o <= a_i and b_i;
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end architecture rtl;
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