16 lines
313 B
VHDL
16 lines
313 B
VHDL
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library ieee;
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use ieee.std_logic_1164.all;
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entity and104 is
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port (
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a_i : in std_logic_vector (103 downto 0);
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b_i : in std_logic_vector (103 downto 0);
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c_o : out std_logic_vector (103 downto 0)
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);
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end entity and104;
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architecture rtl of and104 is
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begin
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c_o <= a_i and b_i;
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end architecture rtl;
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