31 lines
373 B
Coq
31 lines
373 B
Coq
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// Check variable declarations in unnamed blocks
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// All of these should pass in SystemVerilog and all but the last should fail in
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// Verilog
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module test;
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initial begin
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integer x;
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end
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initial begin
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integer x;
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integer y;
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end
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initial begin
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integer x, y;
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end
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initial begin
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integer x;
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integer y;
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x = y;
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end
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initial begin
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$display("PASSED");
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end
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endmodule
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