25 lines
431 B
Coq
25 lines
431 B
Coq
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module top;
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reg ctl, in0, in1;
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wire out3, out4;
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// A UDP can only take two delay values.
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mux2 #(10, 20, 30) q1(out3, ctl, in0, in1);
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mux2 #(10, 20, 30, 40) q2(out4, ctl, in0, in1);
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initial $display("FAILED");
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endmodule
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primitive mux2 (out, ctl, in0, in1);
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output out;
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input ctl, in0, in1;
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table
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0 0 ? : 0;
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0 1 ? : 1;
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1 ? 0 : 0;
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1 ? 1 : 1;
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x 0 0 : 0;
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x 1 1 : 1;
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endtable
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endprimitive
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