46 lines
1.3 KiB
VHDL
46 lines
1.3 KiB
VHDL
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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-- The operation is:
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-- 1) An internal counter is initilaised to zero after a reset is received.
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-- 2) An enable allows an internal running counter to count clock pulses
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-- 3) A tick signal output is generated when a the number of pulses accumulated
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-- are equal to a specified parameter
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entity TimeBase is
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generic (N: in Natural := 12; VALUE: Natural := 1999);
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port(
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CLOCK : in std_logic; -- input clock of 20MHz
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TICK : out std_logic; -- out 1 sec timebase signal
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RESET : in std_logic; -- master reset signal (active high)
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ENABLE : in std_logic;
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COUNT_VALUE: out std_logic_vector (N-1 downto 0)
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);
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end TimeBase;
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architecture TimeBase_rtl of TimeBase is
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signal RunningCounter : std_logic_vector(N-1 downto 0); -- this is the N bit free running counter to allow a big count
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begin
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RunningCounterProcess : process (CLOCK)
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begin
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if ( CLOCK'event and CLOCK = '1') then
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if (RESET = '1') then
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RunningCounter <= (others => '0');
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elsif ( ENABLE = '1') then
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RunningCounter <= RunningCounter + 1;
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end if;
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else
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RunningCounter <= RunningCounter;
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end if;
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end process;
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TICK <= '1' when (RunningCounter = VALUE) else '0';
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COUNT_VALUE <= RunningCounter;
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end TimeBase_rtl;
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