71 lines
1.6 KiB
Coq
71 lines
1.6 KiB
Coq
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/*
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* Modified to add "endtask : <name>" syntax. This modification tests
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* the SystemVerilog extension to the syntax. -- Stephen Williams
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*/
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/*
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* Copyright (c) 2001 Stephan Boettcher <stephan@nevis.columbia.edu>
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*
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* This source code is free software; you can redistribute it
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* and/or modify it in source code form under the terms of the GNU
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* General Public License as published by the Free Software
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* Foundation; either version 2 of the License, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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// $Id: task_scope.v,v 1.1 2001/06/19 13:52:13 ka6s Exp $
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// $Log: task_scope.v,v $
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// Revision 1.1 2001/06/19 13:52:13 ka6s
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// Added 4 tests from Stephan Boettcher
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//
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// Test for task scope lookup in VVP
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module test;
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wire w;
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jobs j(w);
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task ini;
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begin
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j.set(1'bz);
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end
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endtask : ini
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initial
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begin
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ini;
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#1;
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j.set(1'b1);
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#1;
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if (w===1)
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$display("PASSED");
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else
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$display("FAILED");
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end
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endmodule // test
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module jobs (out);
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output out;
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reg out;
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task set;
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input val;
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begin
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#1 out = val;
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end
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endtask : set
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endmodule // jobs
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