24 lines
486 B
Coq
24 lines
486 B
Coq
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module top;
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reg pass = 1'b1;
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reg [14:-1] big = 16'h0123;
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reg signed [15:0] a;
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wire [3:0] w_big = big[a+:4];
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initial begin
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#1; // Wait for the assigns above to happen.
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/* If this fails it is likely because the index width is less
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* than an int width. */
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a = -2;
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#1;
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if (w_big !== 4'b011x) begin
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$display("Failed: .part/v check, expected 4'b011x, got %b.", w_big);
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pass = 1'b0;
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end
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if (pass) $display("PASSED");
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end
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endmodule
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