151 lines
4.4 KiB
Coq
151 lines
4.4 KiB
Coq
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`begin_keywords "1364-2005"
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// -- test force/release of:
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// a wire assigned to a reg
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// a wire with no assignment
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// a whole bus (assigned to a reg),
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// a single bit of a bus (assigned to a reg)
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// -- make sure the force/release is passed into the hierarchy
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//
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// -- run with
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// iverilog -Wall tt.v
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// vvp a.out
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// -- to see debug display statements, use
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// iverilog -Wall -DDISPLAY tt.v
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//
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module top ();
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reg [31:0] ii;
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reg bitfail, bitnafail, busfail, busbitfail;
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reg a;
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reg [1:0] b;
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wire bit = a;
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wire bitna;
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wire [1:0] bus = b;
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wire [1:0] ibus = b;
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wire subfail, subfailna;
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// call in a lower level module
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subtop U1 (
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.subbit(bit),
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.subbus(bus),
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.subfail(subfail)
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);
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subtop U2 (
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.subbit(bitna),
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.subbus(bus),
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.subfail(subfailna)
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);
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initial begin
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a = 1'b1;
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b = 2'b01;
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#5; b = 2'b10;
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#10; b = 2'b11;
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end
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initial begin
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#2;
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force bit = 0;
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force bitna = 0;
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force bus = 0;
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//$display("\n ****** force/release to ibus[0] commented; expect bit[0] failure ******* ");
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force ibus[0] = 0;
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#10;
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release bit;
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force bitna = 1;
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release bus;
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#5;
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release ibus[0];
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end
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initial begin
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bitfail = 0; bitnafail = 0; busfail = 0; busbitfail = 0;
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`ifdef DISPLAY
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$display("");
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$display("expecting bit, bus,ibus to be 1 at T=1");
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$display("then changing to 0 at T=2");
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$display("then bit and bus are 0 from T=3 to T=11, while");
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$display("ibus changes to 2 at T=5 and remains 2 through to T=16");
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$display("bit changes to 1 at T=12 and remains 1 from then on.");
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$display("bus changes to 2 at T=12");
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$display("then 2 from T=13 to T=14");
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$display("then changing to 3 at T=15");
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$display("then 3 from T=16 on");
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$display("ibus changes to 3 at T=17 and remains 3 from then on");
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$display("");
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`endif
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for(ii = 0; ii < 20; ii = ii + 1) begin
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// bit
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if((ii == 1) && (bit !== 1)) bitfail = 1;
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if((ii > 2) && (ii < 12) && (bit !== 0)) bitfail = 1;
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if((ii > 12) && (bit !== 1)) bitfail = 1;
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// bitna
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if((ii == 1) && (bitna !== 1'bz)) bitnafail = 1;
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if((ii > 2) && (ii < 12) && (bitna !== 0)) bitnafail = 1;
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if((ii > 12) && (bitna !== 1)) bitnafail = 1;
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// bus
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if((ii == 1) && (bus !== 1)) busfail = 1;
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if((ii > 2) && (ii < 12) && (bus !== 0)) busfail = 1;
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if((ii > 12) && (ii < 14) && (bus !== 2'b10)) busfail = 1;
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if((ii > 15) && (bus !== 2'b11)) busfail = 1;
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// ibus
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if((ii == 1) && (ibus !== 2'b01)) busbitfail = 1;
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if((ii > 2) && (ii < 4) && (ibus !== 2'b00)) busbitfail = 1;
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if((ii > 5) && (ii < 17) && (ibus !== 2'b10)) busbitfail = 1;
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if((ii > 17) && (ibus !== 2'b11)) busbitfail = 1;
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`ifdef DISPLAY
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$display("time: %0t, a: %b, bit: %b, bitna %b, b: %b, bus: %b, ibus: %b",$time,a,bit,bitna,b,bus,ibus);
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`endif
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#1;
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end
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if(bitfail || bitnafail || busfail || busbitfail || subfail || subfailna) begin
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$display("\n\t--------- force test failed ---------");
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if(bitfail) $display("force to single wire assigned to a reg failed");
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if(bitnafail) $display("force to single unassigned wire failed");
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if(busfail) $display("force to whole of 2-bit bus failed");
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if(busbitfail) $display("force to bit[0] of 2-bit bus failed");
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if(!bitfail && !bitnafail && !busfail && !busbitfail) begin
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if(subfail) $display("force did not affect U1 hierarchy");
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if(subfailna) $display("force did not affect U2 hierarchy");
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end
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$display("\n");
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end else $display("PASSED");
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end
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endmodule
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module subtop(
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subbit,
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subbus,
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subfail
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);
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input subbit;
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input [1:0] subbus;
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output subfail;
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reg subfail;
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reg [31:0] ii;
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initial begin
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subfail = 0;
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for(ii = 0; ii < 20; ii = ii + 1) begin
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// subbit
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if((ii == 1) && (subbit !== 1) && (subbit !== 1'bz)) subfail = 1;
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if((ii > 2) && (ii < 12) && (subbit !== 0)) subfail = 1;
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if((ii > 12) && (subbit !== 1)) subfail = 1;
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// subbus
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if((ii == 1) && (subbus !== 1)) subfail = 1;
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if((ii > 2) && (ii < 12) && (subbus !== 0)) subfail = 1;
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if((ii > 12) && (ii < 14) && (subbus !== 2'b10)) subfail = 1;
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if((ii > 15) && (subbus !== 2'b11)) subfail = 1;
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`ifdef DISPLAY
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$display("\t\t\t\t\ttime: %0t, subbit: %b, subbus: %b",$time,subbit,subbus);
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`endif
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#1;
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end
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end
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endmodule
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`end_keywords
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